{"id":{"repo_id":"uiuc","oai_identifier":"oai:www.ideals.illinois.edu:2142/88932"},"canonical_url":"https://search.dev.ndltd.org/etd/uiuc/oai:www.ideals.illinois.edu:2142/88932","repository":{"repo_id":"uiuc","name":"University of Illinois - Urbana-Champaign","base_url":"https://www.ideals.illinois.edu/oai-pmh"},"display":{"title":"Design of reliable and energy-efficient high-speed interface circuits","abstract":"DSpace SAF Submission Ingestion Package generated from Vireo submission #8656 on 2016-03-02 at 12:48:44","abstract_html":"DSpace SAF Submission Ingestion Package generated from Vireo submission #8656 on 2016-03-02 at 12:48:44","abstract_has_math":false,"creators":["Keel, Min-Sun"],"institution":"University of Illinois at Urbana-Champaign","degree_name":"Ph.D.","degree_level":"Dissertation","degree_discipline":"Electrical & Computer Engineering","degree_department":null,"school":null,"contributors":["Rosenbaum, Elyse","Hanumolu, Pavan Kumar","Schutt-Aine, Jose E.","Shanbhag, Naresh R."],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2016,"date_issued":"2016-03-02T19:32:46Z","date_published":"2016-03-02T19:32:46Z","updated_at":"2026-07-22T22:26:32Z","subjects":["Electrostatic discharge (ESD)","Charged device model (CDM)","High-speed I/O","wireline communication","transmitter","receiver","ADC-based receiver","Stub Series Terminated Logic (SSTL)"],"languages":["en"],"rights":["Copyright 2015 Min-Sun Keel"],"rights_urls":[],"identifier_entries":[]},"links":{"outbound_url":"http://hdl.handle.net/2142/88932","outbound_label":"Handle","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Rosenbaum, Elyse","Hanumolu, Pavan Kumar","Schutt-Aine, Jose E.","Shanbhag, Naresh R."]},{"key":"dc:creator","label":"Author","values":["Keel, Min-Sun"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2016-03-02T19:32:46Z","2015-08-10","2015-12"]},{"key":"dc:type","label":"Dc Type","values":["text"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Electrical & Computer Engineering"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Dissertation"]},{"key":"thesis:degree_name","label":"Degree Name","values":["Ph.D."]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["University of Illinois at Urbana-Champaign"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Electrostatic discharge (ESD)","Charged device model (CDM)","High-speed I/O","wireline communication","transmitter","receiver","ADC-based receiver","Stub Series Terminated Logic (SSTL)"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language","label":"Dc Language","values":["en"]},{"key":"dc:rights","label":"Dc Rights","values":["Copyright 2015 Min-Sun Keel"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["http://hdl.handle.net/2142/88932"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["DSpace SAF Submission Ingestion Package generated from Vireo submission #8656 on 2016-03-02 at 12:48:44","Made available in DSpace on 2016-03-02T19:32:46Z (GMT). No. of bitstreams: 2 KEEL-DISSERTATION-2015.pdf: 8134806 bytes, checksum: ffe087276b2e7d6fdc4150c91eb4633f (MD5) LICENSE.txt: 4209 bytes, checksum: 420208ba0e2970477571cf09e6935677 (MD5) Previous issue date: 2015-08-10","The data-rate demand in high-speed interface circuits increases exponentially every year. High-speed I/Os are better implemented in advanced process technologies for lower-power systems, with the advantages of improved driving capability of the transistors and reduced parasitic capacitance. However, advanced technologies are not necessarily advantageous in terms of device reliability; in particular device failure from electrostatic discharge (ESD) becomes more likely in nano-scale process nodes. In order to secure ESD resiliency, the size of ESD devices on I/O pads should be sufficiently large, which may potentially reduce I/O speed. These two conflicting requirements in high-speed I/O design sometimes require sacrifice to one of the two properties. In this dissertation, three different approaches are proposed to achieve reliable and energy-efficient interface circuits. As the first approach, a novel ESD self-protection scheme to utilize “adaptive active bias conditioning” is proposed to reduce voltage stress on the vulnerable transistors, thereby reducing the burden on ESD protection devices. The second approach is to cancel out effective parasitic capacitance from ESD devices by the T-coil network. Voltage overshoot generated by magnetic coupling of the T-coil network can be suppressed by the proposed “inductance halving” technique, which reduces mutual inductance during ESD. The last approach employs system-level knowledge in the design of an ADC-based receiver for high intersymbol interference (ISI) channels. As a system-level performance metric, bit-error rate (BER) is adopted to mitigate a bit-resolution requirement in “BER-optimal ADC”, which can lead to 2× power-efficiency in the flash ADC and achieve a better BER performance.","Submission original under an indefinite embargo labeled 'Open Access'. The submission was exported from vireo on 2016-03-02 without embargo terms","The student, Min-Sun Keel, accepted the attached license on 2015-08-06 at 22:26.","The student, Min-Sun Keel, submitted this Dissertation for approval on 2015-08-06 at 22:28.","This Dissertation was approved for publication on 2015-08-10 at 13:27."]},{"key":"dc:format","label":"Dc Format","values":["application/pdf"]},{"key":"dc:title","label":"Title","values":["Design of reliable and energy-efficient high-speed interface circuits"]}]}],"canonical_facts":{"dc:contributor":["Rosenbaum, Elyse","Hanumolu, Pavan Kumar","Schutt-Aine, Jose E.","Shanbhag, Naresh R."],"dc:creator":["Keel, Min-Sun"],"dc:date":["2016-03-02T19:32:46Z","2015-08-10","2015-12"],"dc:description":["DSpace SAF Submission Ingestion Package generated from Vireo submission #8656 on 2016-03-02 at 12:48:44","Made available in DSpace on 2016-03-02T19:32:46Z (GMT). No. of bitstreams: 2 KEEL-DISSERTATION-2015.pdf: 8134806 bytes, checksum: ffe087276b2e7d6fdc4150c91eb4633f (MD5) LICENSE.txt: 4209 bytes, checksum: 420208ba0e2970477571cf09e6935677 (MD5) Previous issue date: 2015-08-10","The data-rate demand in high-speed interface circuits increases exponentially every year. High-speed I/Os are better implemented in advanced process technologies for lower-power systems, with the advantages of improved driving capability of the transistors and reduced parasitic capacitance. However, advanced technologies are not necessarily advantageous in terms of device reliability; in particular device failure from electrostatic discharge (ESD) becomes more likely in nano-scale process nodes. In order to secure ESD resiliency, the size of ESD devices on I/O pads should be sufficiently large, which may potentially reduce I/O speed. These two conflicting requirements in high-speed I/O design sometimes require sacrifice to one of the two properties. In this dissertation, three different approaches are proposed to achieve reliable and energy-efficient interface circuits. As the first approach, a novel ESD self-protection scheme to utilize “adaptive active bias conditioning” is proposed to reduce voltage stress on the vulnerable transistors, thereby reducing the burden on ESD protection devices. The second approach is to cancel out effective parasitic capacitance from ESD devices by the T-coil network. Voltage overshoot generated by magnetic coupling of the T-coil network can be suppressed by the proposed “inductance halving” technique, which reduces mutual inductance during ESD. The last approach employs system-level knowledge in the design of an ADC-based receiver for high intersymbol interference (ISI) channels. As a system-level performance metric, bit-error rate (BER) is adopted to mitigate a bit-resolution requirement in “BER-optimal ADC”, which can lead to 2× power-efficiency in the flash ADC and achieve a better BER performance.","Submission original under an indefinite embargo labeled 'Open Access'. The submission was exported from vireo on 2016-03-02 without embargo terms","The student, Min-Sun Keel, accepted the attached license on 2015-08-06 at 22:26.","The student, Min-Sun Keel, submitted this Dissertation for approval on 2015-08-06 at 22:28.","This Dissertation was approved for publication on 2015-08-10 at 13:27."],"dc:format":["application/pdf"],"dc:identifier":["http://hdl.handle.net/2142/88932"],"dc:language":["en"],"dc:rights":["Copyright 2015 Min-Sun Keel"],"dc:subject":["Electrostatic discharge (ESD)","Charged device model (CDM)","High-speed I/O","wireline communication","transmitter","receiver","ADC-based receiver","Stub Series Terminated Logic (SSTL)"],"dc:title":["Design of reliable and energy-efficient high-speed interface circuits"],"dc:type":["text"],"thesis:degree_discipline":["Electrical & Computer Engineering"],"thesis:degree_level":["Dissertation"],"thesis:degree_name":["Ph.D."],"thesis:institution_name":["University of Illinois at Urbana-Champaign"]},"updated_at":"2026-07-22T22:26:32Z"}