{"id":{"repo_id":"uiuc","oai_identifier":"oai:www.ideals.illinois.edu:2142/88219"},"canonical_url":"https://search.dev.ndltd.org/etd/uiuc/oai:www.ideals.illinois.edu:2142/88219","repository":{"repo_id":"uiuc","name":"University of Illinois - Urbana-Champaign","base_url":"https://www.ideals.illinois.edu/oai-pmh"},"display":{"title":"Asymmetric interleaving in low-voltage CMOS power management with multiple supply rails","abstract":"Recent years have seen the proliferation of electronic devices that require multi-phase power converters to provide heterogeneous power rails to different systems. Typical systems will utilize symmetric interleaving as a method of reducing the input current ripple for the power converter. Asymmetric interleaving is a method of control that allows for a further reduction, and in some cases complete cancellation, of this input current ripple. This work looks at some of the challenges for a practical implementation using digital control, and provides results to quantify this improvement. This work demonstrates a control algorithm implementation capable of achieving nearly 3x reduction in the input current ripple via the asymmetric interleaving method.","abstract_html":"Recent years have seen the proliferation of electronic devices that require multi-phase power converters to provide heterogeneous power rails to different systems. Typical systems will utilize symmetric interleaving as a method of reducing the input current ripple for the power converter. Asymmetric interleaving is a method of control that allows for a further reduction, and in some cases complete cancellation, of this input current ripple. This work looks at some of the challenges for a practical implementation using digital control, and provides results to quantify this improvement. This work demonstrates a control algorithm implementation capable of achieving nearly 3x reduction in the input current ripple via the asymmetric interleaving method.","abstract_has_math":false,"creators":["Ho, Aaron Daniel"],"institution":"University of Illinois at Urbana-Champaign","degree_name":"M.S.","degree_level":"Thesis","degree_discipline":"Electrical & Computer Engineering","degree_department":null,"school":null,"contributors":["Pilawa-Podgurski, Robert C."],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2015,"date_issued":"2015-09-29T20:50:21Z","date_published":"2015-09-29T20:50:21Z","updated_at":"2026-07-22T22:26:31Z","subjects":["complementary metal–oxide–semiconductor (CMOS) integrated circuits","digital control","low-power electronics","power convertors","asymmetric interleaving","heterogeneous power rails","low voltage complementary metal–oxide–semiconductor (CMOS) power management","multiphase (complementary metal–oxide–semiconductor) CMOS power management IC system","multiphase power converters","multiple supply rails","reduced input current ripple","size 180 nm","Hardware","Mathematical model","Prototypes","Table lookup","Time-domain analysis"],"languages":["en"],"rights":["Copyright 2015 Aaron Daniel Ho"],"rights_urls":[],"identifier_entries":[]},"links":{"outbound_url":"http://hdl.handle.net/2142/88219","outbound_label":"Handle","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Pilawa-Podgurski, Robert C."]},{"key":"dc:creator","label":"Author","values":["Ho, Aaron Daniel"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2015-09-29T20:50:21Z","2017-09-30T09:15:30Z","2015-08","2015-07-21","2015-8"]},{"key":"dc:type","label":"Dc Type","values":["text"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Electrical & Computer Engineering"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Thesis"]},{"key":"thesis:degree_name","label":"Degree Name","values":["M.S."]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["University of Illinois at Urbana-Champaign"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["complementary metal–oxide–semiconductor (CMOS) integrated circuits","digital control","low-power electronics","power convertors","asymmetric interleaving","heterogeneous power rails","low voltage complementary metal–oxide–semiconductor (CMOS) power management","multiphase (complementary metal–oxide–semiconductor) CMOS power management IC system","multiphase power converters","multiple supply rails","reduced input current ripple","size 180 nm","Hardware","Mathematical model","Prototypes","Table lookup","Time-domain analysis"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language","label":"Dc Language","values":["en"]},{"key":"dc:rights","label":"Dc Rights","values":["Copyright 2015 Aaron Daniel Ho"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["http://hdl.handle.net/2142/88219"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["Recent years have seen the proliferation of electronic devices that require multi-phase power converters to provide heterogeneous power rails to different systems. Typical systems will utilize symmetric interleaving as a method of reducing the input current ripple for the power converter. Asymmetric interleaving is a method of control that allows for a further reduction, and in some cases complete cancellation, of this input current ripple. This work looks at some of the challenges for a practical implementation using digital control, and provides results to quantify this improvement. This work demonstrates a control algorithm implementation capable of achieving nearly 3x reduction in the input current ripple via the asymmetric interleaving method.","Submission published under a 24 month embargo labeled 'U of I only', the embargo will last until 2017-08-01","The student, Aaron Ho, accepted the attached license on 2015-07-20 at 11:34.","The student, Aaron Ho, submitted this Thesis for approval on 2015-07-20 at 11:40.","This Thesis was approved for publication on 2015-07-21 at 13:32.","DSpace SAF Submission Ingestion Package generated from Vireo submission #8561 on 2015-09-29 at 15:00:52","Made available in DSpace on 2015-09-29T20:50:21Z (GMT). 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Typical systems will utilize symmetric interleaving as a method of reducing the input current ripple for the power converter. Asymmetric interleaving is a method of control that allows for a further reduction, and in some cases complete cancellation, of this input current ripple. This work looks at some of the challenges for a practical implementation using digital control, and provides results to quantify this improvement. This work demonstrates a control algorithm implementation capable of achieving nearly 3x reduction in the input current ripple via the asymmetric interleaving method.","Submission published under a 24 month embargo labeled 'U of I only', the embargo will last until 2017-08-01","The student, Aaron Ho, accepted the attached license on 2015-07-20 at 11:34.","The student, Aaron Ho, submitted this Thesis for approval on 2015-07-20 at 11:40.","This Thesis was approved for publication on 2015-07-21 at 13:32.","DSpace SAF Submission Ingestion Package generated from Vireo submission #8561 on 2015-09-29 at 15:00:52","Made available in DSpace on 2015-09-29T20:50:21Z (GMT). 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