{"id":{"repo_id":"uiuc","oai_identifier":"oai:www.ideals.illinois.edu:2142/87964"},"canonical_url":"https://search.dev.ndltd.org/etd/uiuc/oai:www.ideals.illinois.edu:2142/87964","repository":{"repo_id":"uiuc","name":"University of Illinois - Urbana-Champaign","base_url":"https://www.ideals.illinois.edu/oai-pmh"},"display":{"title":"Modeling and simulation of full-component integrated circuits in transient ESD events","abstract":"This thesis presents a methodology to model and simulate transient electrostatic discharge (ESD) responses of integrated circuits (IC). To obtain valid simulation results, the IC component must be represented by a circuit netlist composed of device models that are valid under the ESD conditions. Models of the nonlinear devices that make up the ESD protection network of the IC must have transient I-V responses calibrated against measurements that emulate ESD events. Interconnects, power distribution networks, and the silicon substrate on the chip die as well as on the IC package must be faithfully constructed to emulate the fact that ESD current flows in a distributed manner across the entire IC component. The resultant equivalent circuit model therefore contains a huge number of nodes and devices, and the simulation runtime may be prohibitively long. Techniques must be devised to make the numerical simulation process more efficient without sacrifice of accuracy. These techniques include reasonable abstraction of the distributed full-component circuit netlist, dynamic piecewise-linear device models, and customized efficient transient circuit simulator. With the simulation streamlining techniques set up properly, comprehensive and predictive transient ESD simulation can be carried out efficiently to investigate the weakest link in the target IC, and the design can be fine-tuned to achieve optimal performance in both functionality and ESD reliability.","abstract_html":"This thesis presents a methodology to model and simulate transient electrostatic discharge (ESD) responses of integrated circuits (IC). To obtain valid simulation results, the IC component must be represented by a circuit netlist composed of device models that are valid under the ESD conditions. Models of the nonlinear devices that make up the ESD protection network of the IC must have transient I-V responses calibrated against measurements that emulate ESD events. Interconnects, power distribution networks, and the silicon substrate on the chip die as well as on the IC package must be faithfully constructed to emulate the fact that ESD current flows in a distributed manner across the entire IC component. The resultant equivalent circuit model therefore contains a huge number of nodes and devices, and the simulation runtime may be prohibitively long. Techniques must be devised to make the numerical simulation process more efficient without sacrifice of accuracy. These techniques include reasonable abstraction of the distributed full-component circuit netlist, dynamic piecewise-linear device models, and customized efficient transient circuit simulator. With the simulation streamlining techniques set up properly, comprehensive and predictive transient ESD simulation can be carried out efficiently to investigate the weakest link in the target IC, and the design can be fine-tuned to achieve optimal performance in both functionality and ESD reliability.","abstract_has_math":false,"creators":["Meng, Kuo-Hsuan"],"institution":"University of Illinois at Urbana-Champaign","degree_name":"Ph.D.","degree_level":"Dissertation","degree_discipline":"Electrical & Computer Engineering","degree_department":null,"school":null,"contributors":["Rosenbaum, Elyse","Chen, Deming","Schutt-Ainé, José E.","Wong, Martin D.F."],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2015,"date_issued":"2015-09-29T20:37:44Z","date_published":"2015-09-29T20:37:44Z","updated_at":"2026-07-22T22:26:31Z","subjects":["Electrostatic Discharge (ESD)","Circuit Simulation","Compact Modeling","Full-component Model","Piecewise-linear Behavior Model","ESD metal–oxide–semiconductor field-effect transistor (MOSFET)","ESD Diode","Numerical Circuit Analysis","Simulator"],"languages":["en"],"rights":["Copyright 2015 Kuo-Hsuan Meng"],"rights_urls":[],"identifier_entries":[]},"links":{"outbound_url":"http://hdl.handle.net/2142/87964","outbound_label":"Handle","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Rosenbaum, Elyse","Chen, Deming","Schutt-Ainé, José E.","Wong, Martin D.F."]},{"key":"dc:creator","label":"Author","values":["Meng, Kuo-Hsuan"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2015-09-29T20:37:44Z","2015-08","2015-06-17","2015-8"]},{"key":"dc:type","label":"Dc Type","values":["text"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Electrical & Computer Engineering"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Dissertation"]},{"key":"thesis:degree_name","label":"Degree Name","values":["Ph.D."]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["University of Illinois at Urbana-Champaign"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Electrostatic Discharge (ESD)","Circuit Simulation","Compact Modeling","Full-component Model","Piecewise-linear Behavior Model","ESD metal–oxide–semiconductor field-effect transistor (MOSFET)","ESD Diode","Numerical Circuit Analysis","Simulator"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language","label":"Dc Language","values":["en"]},{"key":"dc:rights","label":"Dc Rights","values":["Copyright 2015 Kuo-Hsuan Meng"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["http://hdl.handle.net/2142/87964"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["This thesis presents a methodology to model and simulate transient electrostatic discharge (ESD) responses of integrated circuits (IC). To obtain valid simulation results, the IC component must be represented by a circuit netlist composed of device models that are valid under the ESD conditions. Models of the nonlinear devices that make up the ESD protection network of the IC must have transient I-V responses calibrated against measurements that emulate ESD events. Interconnects, power distribution networks, and the silicon substrate on the chip die as well as on the IC package must be faithfully constructed to emulate the fact that ESD current flows in a distributed manner across the entire IC component. The resultant equivalent circuit model therefore contains a huge number of nodes and devices, and the simulation runtime may be prohibitively long. Techniques must be devised to make the numerical simulation process more efficient without sacrifice of accuracy. These techniques include reasonable abstraction of the distributed full-component circuit netlist, dynamic piecewise-linear device models, and customized efficient transient circuit simulator. With the simulation streamlining techniques set up properly, comprehensive and predictive transient ESD simulation can be carried out efficiently to investigate the weakest link in the target IC, and the design can be fine-tuned to achieve optimal performance in both functionality and ESD reliability.","Submission original under an indefinite embargo labeled 'Open Access'. The submission was exported from vireo on 2015-09-29 without embargo terms","The student, Kuo-Hsuan Meng, accepted the attached license on 2015-06-15 at 15:36.","The student, Kuo-Hsuan Meng, submitted this Dissertation for approval on 2015-06-15 at 15:46.","This Dissertation was approved for publication on 2015-06-17 at 11:57.","DSpace SAF Submission Ingestion Package generated from Vireo submission #8280 on 2015-09-29 at 13:21:28","Made available in DSpace on 2015-09-29T20:37:44Z (GMT). No. of bitstreams: 2 MENG-DISSERTATION-2015.pdf: 10030693 bytes, checksum: d1fba182381a760efe4fec6606d35ad9 (MD5) LICENSE.txt: 4211 bytes, checksum: d41ec47fca4315d38adcf748c887dd89 (MD5) Previous issue date: 2015-06-17"]},{"key":"dc:format","label":"Dc Format","values":["application/pdf"]},{"key":"dc:title","label":"Title","values":["Modeling and simulation of full-component integrated circuits in transient ESD events"]}]}],"canonical_facts":{"dc:contributor":["Rosenbaum, Elyse","Chen, Deming","Schutt-Ainé, José E.","Wong, Martin D.F."],"dc:creator":["Meng, Kuo-Hsuan"],"dc:date":["2015-09-29T20:37:44Z","2015-08","2015-06-17","2015-8"],"dc:description":["This thesis presents a methodology to model and simulate transient electrostatic discharge (ESD) responses of integrated circuits (IC). To obtain valid simulation results, the IC component must be represented by a circuit netlist composed of device models that are valid under the ESD conditions. Models of the nonlinear devices that make up the ESD protection network of the IC must have transient I-V responses calibrated against measurements that emulate ESD events. Interconnects, power distribution networks, and the silicon substrate on the chip die as well as on the IC package must be faithfully constructed to emulate the fact that ESD current flows in a distributed manner across the entire IC component. The resultant equivalent circuit model therefore contains a huge number of nodes and devices, and the simulation runtime may be prohibitively long. Techniques must be devised to make the numerical simulation process more efficient without sacrifice of accuracy. These techniques include reasonable abstraction of the distributed full-component circuit netlist, dynamic piecewise-linear device models, and customized efficient transient circuit simulator. With the simulation streamlining techniques set up properly, comprehensive and predictive transient ESD simulation can be carried out efficiently to investigate the weakest link in the target IC, and the design can be fine-tuned to achieve optimal performance in both functionality and ESD reliability.","Submission original under an indefinite embargo labeled 'Open Access'. The submission was exported from vireo on 2015-09-29 without embargo terms","The student, Kuo-Hsuan Meng, accepted the attached license on 2015-06-15 at 15:36.","The student, Kuo-Hsuan Meng, submitted this Dissertation for approval on 2015-06-15 at 15:46.","This Dissertation was approved for publication on 2015-06-17 at 11:57.","DSpace SAF Submission Ingestion Package generated from Vireo submission #8280 on 2015-09-29 at 13:21:28","Made available in DSpace on 2015-09-29T20:37:44Z (GMT). No. of bitstreams: 2 MENG-DISSERTATION-2015.pdf: 10030693 bytes, checksum: d1fba182381a760efe4fec6606d35ad9 (MD5) LICENSE.txt: 4211 bytes, checksum: d41ec47fca4315d38adcf748c887dd89 (MD5) Previous issue date: 2015-06-17"],"dc:format":["application/pdf"],"dc:identifier":["http://hdl.handle.net/2142/87964"],"dc:language":["en"],"dc:rights":["Copyright 2015 Kuo-Hsuan Meng"],"dc:subject":["Electrostatic Discharge (ESD)","Circuit Simulation","Compact Modeling","Full-component Model","Piecewise-linear Behavior Model","ESD metal–oxide–semiconductor field-effect transistor (MOSFET)","ESD Diode","Numerical Circuit Analysis","Simulator"],"dc:title":["Modeling and simulation of full-component integrated circuits in transient ESD events"],"dc:type":["text"],"thesis:degree_discipline":["Electrical & Computer Engineering"],"thesis:degree_level":["Dissertation"],"thesis:degree_name":["Ph.D."],"thesis:institution_name":["University of Illinois at Urbana-Champaign"]},"updated_at":"2026-07-22T22:26:31Z"}