{"id":{"repo_id":"uiuc","oai_identifier":"oai:www.ideals.illinois.edu:2142/81959"},"canonical_url":"https://search.dev.ndltd.org/etd/uiuc/oai:www.ideals.illinois.edu:2142/81959","repository":{"repo_id":"uiuc","name":"University of Illinois - Urbana-Champaign","base_url":"https://www.ideals.illinois.edu/oai-pmh"},"display":{"title":"An Intelligent Memory for Data -Parallel Applications","abstract":"U of I Only","abstract_html":"U of I Only","abstract_has_math":false,"creators":["Kang, Yi"],"institution":"University of Illinois at Urbana-Champaign","degree_name":"Ph.D.","degree_level":"Dissertation","degree_discipline":"Computer Science","degree_department":null,"school":null,"contributors":["Torrellas, Josep"],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2015,"date_issued":"2015-09-25T20:21:11Z","date_published":"2015-09-25T20:21:11Z","updated_at":"2026-07-22T22:26:17Z","subjects":["Engineering, Electronics and Electrical"],"languages":["eng"],"rights":[],"rights_urls":[],"identifier_entries":[{"key":"dc:identifier","label":"Identifier","values":["(MiAaPQ)AAI9953057"],"render_values":[{"text":"(MiAaPQ)AAI9953057","href":null,"code":true}]}]},"links":{"outbound_url":"http://hdl.handle.net/2142/81959","outbound_label":"Handle","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Torrellas, Josep"]},{"key":"dc:creator","label":"Author","values":["Kang, Yi"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2015-09-25T20:21:11Z","10000-01-01","1999"]},{"key":"dc:type","label":"Dc Type","values":["text"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Computer Science"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Dissertation"]},{"key":"thesis:degree_name","label":"Degree Name","values":["Ph.D."]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["University of Illinois at Urbana-Champaign"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Engineering, Electronics and Electrical"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language","label":"Dc Language","values":["eng"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["http://hdl.handle.net/2142/81959","(MiAaPQ)AAI9953057"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["U of I Only","Many research issues related to FlexRAM are discussed. We describe the FlexRAM architecture include memory architecture, processor architecture and communication models. The rationales for our architecture design are based on general principles and constraints from the technology and existing computer systems. We address design issues arising from the FlexRAM logical and physical design. We show that it is feasible to implement a FlexRAM chip under current MLD technology by setting up HDL models for a FlexRAM chip and estimating its physical parameters. Evaluations based on high-level simulation are made. Decent speedup numbers are shown that FlexRAM architecture is effective for many data-parallel applications. How to program FlexRAM is also explored and a new programming model for IRAM---Intelligent Memory Operation is suggested. We identify and analyze a range of real applications for FlexRAM, including applications in the domain of data mining, computational biology, decision support and multimedia.","Made available in DSpace on 2015-09-25T20:21:11Z (GMT). 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