{"id":{"repo_id":"uiuc","oai_identifier":"oai:www.ideals.illinois.edu:2142/81909"},"canonical_url":"https://search.dev.ndltd.org/etd/uiuc/oai:www.ideals.illinois.edu:2142/81909","repository":{"repo_id":"uiuc","name":"University of Illinois - Urbana-Champaign","base_url":"https://www.ideals.illinois.edu/oai-pmh"},"display":{"title":"Efficient Equivalence Checking in a Modular Design Environment","abstract":"We address the issue of transforming multi-phase designs, a popular industry practice to equivalent one-phase designs to enable the application of the current equivalence checking techniques. We propose an algorithm to compute the steady states of a machine by relaxing the assumption of a designated set of initial states (DIS). This assumption is used in research but is often restrictive in an industrial design environment. We use the paradigm of sequential hardware equivalence (SHE), which does not make the DIS assumption, for checking the equivalence of two machines. We show that two machines are SHE if the outputs of their product machine are 0 in the steady states. We propose machine partitioning and minimum area retiming to alleviate the problem of large state spaces common in industrial designs. Our techniques result in exponential reductions in the state space and enable equivalence checking of machines which cannot be handled otherwise. Lastly, we address the issue of interface verification arising out of a modular design environment. We show that the constraints required to express the input don't care space for equivalence checking of a module need to be verified formally for the completeness of equivalence checking. We characterize these constraints as combinationally provable and sequentially provable. Subsequently, we develop an assertion checking framework with efficient techniques to handle both types of constraints.","abstract_html":"We address the issue of transforming multi-phase designs, a popular industry practice to equivalent one-phase designs to enable the application of the current equivalence checking techniques. We propose an algorithm to compute the steady states of a machine by relaxing the assumption of a designated set of initial states (DIS). This assumption is used in research but is often restrictive in an industrial design environment. We use the paradigm of sequential hardware equivalence (SHE), which does not make the DIS assumption, for checking the equivalence of two machines. We show that two machines are SHE if the outputs of their product machine are 0 in the steady states. We propose machine partitioning and minimum area retiming to alleviate the problem of large state spaces common in industrial designs. Our techniques result in exponential reductions in the state space and enable equivalence checking of machines which cannot be handled otherwise. Lastly, we address the issue of interface verification arising out of a modular design environment. We show that the constraints required to express the input don't care space for equivalence checking of a module need to be verified formally for the completeness of equivalence checking. We characterize these constraints as combinationally provable and sequentially provable. Subsequently, we develop an assertion checking framework with efficient techniques to handle both types of constraints.","abstract_has_math":false,"creators":["Hasteer, Gagan"],"institution":"University of Illinois at Urbana-Champaign","degree_name":"Ph.D.","degree_level":"Dissertation","degree_discipline":"Computer Science","degree_department":null,"school":null,"contributors":["Banerjee, Prithviraj"],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2015,"date_issued":"2015-09-25T20:20:57Z","date_published":"2015-09-25T20:20:57Z","updated_at":"2026-07-22T22:26:17Z","subjects":["Computer Science"],"languages":["eng"],"rights":[],"rights_urls":[],"identifier_entries":[{"key":"dc:identifier","label":"Identifier","values":["(MiAaPQ)AAI9834686"],"render_values":[{"text":"(MiAaPQ)AAI9834686","href":null,"code":true}]}]},"links":{"outbound_url":"http://hdl.handle.net/2142/81909","outbound_label":"Handle","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Banerjee, Prithviraj"]},{"key":"dc:creator","label":"Author","values":["Hasteer, Gagan"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2015-09-25T20:20:57Z","10000-01-01","1998"]},{"key":"dc:type","label":"Dc Type","values":["text"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Computer Science"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Dissertation"]},{"key":"thesis:degree_name","label":"Degree Name","values":["Ph.D."]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["University of Illinois at Urbana-Champaign"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Computer Science"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language","label":"Dc Language","values":["eng"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["http://hdl.handle.net/2142/81909","(MiAaPQ)AAI9834686"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["We address the issue of transforming multi-phase designs, a popular industry practice to equivalent one-phase designs to enable the application of the current equivalence checking techniques. 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We show that the constraints required to express the input don't care space for equivalence checking of a module need to be verified formally for the completeness of equivalence checking. We characterize these constraints as combinationally provable and sequentially provable. Subsequently, we develop an assertion checking framework with efficient techniques to handle both types of constraints.","Made available in DSpace on 2015-09-25T20:20:57Z (GMT). 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