{"id":{"repo_id":"uiuc","oai_identifier":"oai:www.ideals.illinois.edu:2142/81775"},"canonical_url":"https://search.dev.ndltd.org/etd/uiuc/oai:www.ideals.illinois.edu:2142/81775","repository":{"repo_id":"uiuc","name":"University of Illinois - Urbana-Champaign","base_url":"https://www.ideals.illinois.edu/oai-pmh"},"display":{"title":"Novel CAD Techniques for New Challenges in Deep Sub-Micron VLSI Design","abstract":"In Chapter 2, we present a floorplanning algorithm for 3-D IC designs, which can effectively reduce interconnect delays. Our algorithm is based on a generalization of the classical 2-D slicing floorplans to 3-D slicing floorplans. A new encoding scheme of slicing floorplans (2-D/3-D) and its associated set of moves form the basis of the new simulated annealing based algorithm. In Chapter 3, we present the first FPGA floorplanning algorithm targeted for FPGAs with heterogeneous resources, such as Configurable Logic Blocks ( CLB), RAMs and multipliers. In Chapter 4, we present an efficient and effective method to reduce circuit leakage power consumption using input vector control. Our algorithm is able to solve the IVC and gate replacement problems simultaneously. A dynamic programming based-algorithm is used for making fast evaluation on input vectors, as well as replacing gates. In Chapter 5, we present an FPGA technology snapping algorithm targeting dynamic power minimization. We propose a switching activity estimation model considering glitches for FPGAs, and develop our technology mapping algorithm based on this model. In Chapter 6, we present an FPGA technology mapping algorithm targeting designs with multi-clock domains such as those containing multi-clocks, multi-cycle paths, and false paths. We use timing constraints to handle these unique clocking issues. Our algorithm produces a mapped circuit with the optimal mapping depth under timing constraints. In chapter 7, we target FPGA performance optimization using a novel BDD-based synthesis approach. In this work, we concentrate on delay reduction and conclude that there is a large optimization margin through BDD synthesis for FPGA performance optimization.","abstract_html":"In Chapter 2, we present a floorplanning algorithm for 3-D IC designs, which can effectively reduce interconnect delays. Our algorithm is based on a generalization of the classical 2-D slicing floorplans to 3-D slicing floorplans. A new encoding scheme of slicing floorplans (2-D/3-D) and its associated set of moves form the basis of the new simulated annealing based algorithm. In Chapter 3, we present the first FPGA floorplanning algorithm targeted for FPGAs with heterogeneous resources, such as Configurable Logic Blocks ( CLB), RAMs and multipliers. In Chapter 4, we present an efficient and effective method to reduce circuit leakage power consumption using input vector control. Our algorithm is able to solve the IVC and gate replacement problems simultaneously. A dynamic programming based-algorithm is used for making fast evaluation on input vectors, as well as replacing gates. In Chapter 5, we present an FPGA technology snapping algorithm targeting dynamic power minimization. We propose a switching activity estimation model considering glitches for FPGAs, and develop our technology mapping algorithm based on this model. In Chapter 6, we present an FPGA technology mapping algorithm targeting designs with multi-clock domains such as those containing multi-clocks, multi-cycle paths, and false paths. We use timing constraints to handle these unique clocking issues. Our algorithm produces a mapped circuit with the optimal mapping depth under timing constraints. In chapter 7, we target FPGA performance optimization using a novel BDD-based synthesis approach. In this work, we concentrate on delay reduction and conclude that there is a large optimization margin through BDD synthesis for FPGA performance optimization.","abstract_has_math":false,"creators":["Cheng, Lei"],"institution":"University of Illinois at Urbana-Champaign","degree_name":"Ph.D.","degree_level":"Dissertation","degree_discipline":"Computer Science","degree_department":null,"school":null,"contributors":["Wong, Martin D.F.","Chen, Deming"],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2015,"date_issued":"2015-09-25T20:20:24Z","date_published":"2015-09-25T20:20:24Z","updated_at":"2026-07-22T22:26:16Z","subjects":["Computer Science"],"languages":["eng"],"rights":[],"rights_urls":[],"identifier_entries":[{"key":"dc:identifier","label":"Identifier","values":["(MiAaPQ)AAI3290202"],"render_values":[{"text":"(MiAaPQ)AAI3290202","href":null,"code":true}]}]},"links":{"outbound_url":"http://hdl.handle.net/2142/81775","outbound_label":"Handle","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Wong, Martin D.F.","Chen, Deming"]},{"key":"dc:creator","label":"Author","values":["Cheng, Lei"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2015-09-25T20:20:24Z","10000-01-01","2007"]},{"key":"dc:type","label":"Dc Type","values":["text"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Computer Science"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Dissertation"]},{"key":"thesis:degree_name","label":"Degree Name","values":["Ph.D."]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["University of Illinois at Urbana-Champaign"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Computer Science"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language","label":"Dc Language","values":["eng"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["http://hdl.handle.net/2142/81775","(MiAaPQ)AAI3290202"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["In Chapter 2, we present a floorplanning algorithm for 3-D IC designs, which can effectively reduce interconnect delays. Our algorithm is based on a generalization of the classical 2-D slicing floorplans to 3-D slicing floorplans. A new encoding scheme of slicing floorplans (2-D/3-D) and its associated set of moves form the basis of the new simulated annealing based algorithm. In Chapter 3, we present the first FPGA floorplanning algorithm targeted for FPGAs with heterogeneous resources, such as Configurable Logic Blocks ( CLB), RAMs and multipliers. In Chapter 4, we present an efficient and effective method to reduce circuit leakage power consumption using input vector control. Our algorithm is able to solve the IVC and gate replacement problems simultaneously. A dynamic programming based-algorithm is used for making fast evaluation on input vectors, as well as replacing gates. In Chapter 5, we present an FPGA technology snapping algorithm targeting dynamic power minimization. We propose a switching activity estimation model considering glitches for FPGAs, and develop our technology mapping algorithm based on this model. In Chapter 6, we present an FPGA technology mapping algorithm targeting designs with multi-clock domains such as those containing multi-clocks, multi-cycle paths, and false paths. We use timing constraints to handle these unique clocking issues. Our algorithm produces a mapped circuit with the optimal mapping depth under timing constraints. In chapter 7, we target FPGA performance optimization using a novel BDD-based synthesis approach. In this work, we concentrate on delay reduction and conclude that there is a large optimization margin through BDD synthesis for FPGA performance optimization.","Made available in DSpace on 2015-09-25T20:20:24Z (GMT). No. of bitstreams: 2 license.txt: 4848 bytes, checksum: 96035ab3f5e1c23cc7138a224ce498bd (MD5) 3290202.pdf: 4028915 bytes, checksum: 6ff921bdf917812b6807d934d2bc3537 (MD5) Previous issue date: 2007","Embargo set by: Seth Robbins for item 83056 Lift date: Forever Reason: Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs","Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs","U of I Only","147 p.","Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 2007."]},{"key":"dc:title","label":"Title","values":["Novel CAD Techniques for New Challenges in Deep Sub-Micron VLSI Design"]}]}],"canonical_facts":{"dc:contributor":["Wong, Martin D.F.","Chen, Deming"],"dc:creator":["Cheng, Lei"],"dc:date":["2015-09-25T20:20:24Z","10000-01-01","2007"],"dc:description":["In Chapter 2, we present a floorplanning algorithm for 3-D IC designs, which can effectively reduce interconnect delays. Our algorithm is based on a generalization of the classical 2-D slicing floorplans to 3-D slicing floorplans. A new encoding scheme of slicing floorplans (2-D/3-D) and its associated set of moves form the basis of the new simulated annealing based algorithm. In Chapter 3, we present the first FPGA floorplanning algorithm targeted for FPGAs with heterogeneous resources, such as Configurable Logic Blocks ( CLB), RAMs and multipliers. In Chapter 4, we present an efficient and effective method to reduce circuit leakage power consumption using input vector control. Our algorithm is able to solve the IVC and gate replacement problems simultaneously. A dynamic programming based-algorithm is used for making fast evaluation on input vectors, as well as replacing gates. In Chapter 5, we present an FPGA technology snapping algorithm targeting dynamic power minimization. We propose a switching activity estimation model considering glitches for FPGAs, and develop our technology mapping algorithm based on this model. In Chapter 6, we present an FPGA technology mapping algorithm targeting designs with multi-clock domains such as those containing multi-clocks, multi-cycle paths, and false paths. We use timing constraints to handle these unique clocking issues. Our algorithm produces a mapped circuit with the optimal mapping depth under timing constraints. In chapter 7, we target FPGA performance optimization using a novel BDD-based synthesis approach. In this work, we concentrate on delay reduction and conclude that there is a large optimization margin through BDD synthesis for FPGA performance optimization.","Made available in DSpace on 2015-09-25T20:20:24Z (GMT). No. of bitstreams: 2 license.txt: 4848 bytes, checksum: 96035ab3f5e1c23cc7138a224ce498bd (MD5) 3290202.pdf: 4028915 bytes, checksum: 6ff921bdf917812b6807d934d2bc3537 (MD5) Previous issue date: 2007","Embargo set by: Seth Robbins for item 83056 Lift date: Forever Reason: Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs","Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs","U of I Only","147 p.","Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 2007."],"dc:identifier":["http://hdl.handle.net/2142/81775","(MiAaPQ)AAI3290202"],"dc:language":["eng"],"dc:subject":["Computer Science"],"dc:title":["Novel CAD Techniques for New Challenges in Deep Sub-Micron VLSI Design"],"dc:type":["text"],"thesis:degree_discipline":["Computer Science"],"thesis:degree_level":["Dissertation"],"thesis:degree_name":["Ph.D."],"thesis:institution_name":["University of Illinois at Urbana-Champaign"]},"updated_at":"2026-07-22T22:26:16Z"}