{"id":{"repo_id":"uiuc","oai_identifier":"oai:www.ideals.illinois.edu:2142/81355"},"canonical_url":"https://search.dev.ndltd.org/etd/uiuc/oai:www.ideals.illinois.edu:2142/81355","repository":{"repo_id":"uiuc","name":"University of Illinois - Urbana-Champaign","base_url":"https://www.ideals.illinois.edu/oai-pmh"},"display":{"title":"Crosstalk Noise and Timing Analysis of Digital VLSI Circuits With Coupled Interconnects","abstract":"109 p.","abstract_html":"109 p.","abstract_has_math":false,"creators":["Lu, Ninglong"],"institution":"University of Illinois at Urbana-Champaign","degree_name":"Ph.D.","degree_level":"Dissertation","degree_discipline":"Electrical Engineering","degree_department":null,"school":null,"contributors":["Hajj, Ibrahim N."],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2015,"date_issued":"2015-09-25T20:10:42Z","date_published":"2015-09-25T20:10:42Z","updated_at":"2026-07-22T22:26:16Z","subjects":["Engineering, Electronics and Electrical"],"languages":["eng"],"rights":[],"rights_urls":[],"identifier_entries":[{"key":"dc:identifier","label":"Identifier","values":["(MiAaPQ)AAI9990067"],"render_values":[{"text":"(MiAaPQ)AAI9990067","href":null,"code":true}]}]},"links":{"outbound_url":"http://hdl.handle.net/2142/81355","outbound_label":"Handle","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Hajj, Ibrahim N."]},{"key":"dc:creator","label":"Author","values":["Lu, Ninglong"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2015-09-25T20:10:42Z","10000-01-01","2000"]},{"key":"dc:type","label":"Dc Type","values":["text"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Electrical Engineering"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Dissertation"]},{"key":"thesis:degree_name","label":"Degree Name","values":["Ph.D."]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["University of Illinois at Urbana-Champaign"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Engineering, Electronics and Electrical"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language","label":"Dc Language","values":["eng"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["http://hdl.handle.net/2142/81355","(MiAaPQ)AAI9990067"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["109 p.","At the logic hierarchical level, we have developed a logic-level timing analyzer that will perform static timing simulation as well m coupling noise estimation using the information produced during the circuit hierarchy stage. The results of this analyzer consist of (a) critical path delay for the entire circuit, (b) transition windows, and (c) crosstalk noises for all victim gates. The maximum amplitude and effective width of crosstalk can be obtained at the fan-out of each victim gate and used to check the failure criteria of the gate that receives this noise pulse as an input.","Made available in DSpace on 2015-09-25T20:10:42Z (GMT). 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The results of this analyzer consist of (a) critical path delay for the entire circuit, (b) transition windows, and (c) crosstalk noises for all victim gates. The maximum amplitude and effective width of crosstalk can be obtained at the fan-out of each victim gate and used to check the failure criteria of the gate that receives this noise pulse as an input.","Made available in DSpace on 2015-09-25T20:10:42Z (GMT). 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