{"id":{"repo_id":"uiuc","oai_identifier":"oai:www.ideals.illinois.edu:2142/81213"},"canonical_url":"https://search.dev.ndltd.org/etd/uiuc/oai:www.ideals.illinois.edu:2142/81213","repository":{"repo_id":"uiuc","name":"University of Illinois - Urbana-Champaign","base_url":"https://www.ideals.illinois.edu/oai-pmh"},"display":{"title":"Low-Spurious Analog-to-Digital Conversion Using Multi-Stage Code-Error Calibration","abstract":"This thesis presents a 5-5-5-6b pipelined ADC architecture that alleviates the requirements for initial capacitor matching and residue amplifier settling accuracy. The two 5-bit MSB stages are digitally calibrated to implement a 15-bit, 5 Msample/s low-spurious ADC using 1.4 $\\mu$m CMOS. A skip-and-fill algorithm with non-linear interpolation also opens up the possibility of calibrating ADCs in the background synchronously with their normal operations. Interpolation results for the background calibration are compared with the foreground calibration results. The prototype ADC exhibits a DNL of +0.75/$-$0.6 LSB, an INL of +1.77/$-$1.58 LSB, and all spurious components are suppressed to below $-$93 dB when sampled at 5 MHz. The chip occupies an active area of 27 mm$\\sp2,$ and the analog part consumes 60 mW at 5 V. Memory and arithmetic units for calibration are supplied externally in testing.","abstract_html":"This thesis presents a 5-5-5-6b pipelined ADC architecture that alleviates the requirements for initial capacitor matching and residue amplifier settling accuracy. The two 5-bit MSB stages are digitally calibrated to implement a 15-bit, 5 Msample/s low-spurious ADC using 1.4 <span class=\"etd-inline-math\">&mu;</span>m CMOS. A skip-and-fill algorithm with non-linear interpolation also opens up the possibility of calibrating ADCs in the background synchronously with their normal operations. Interpolation results for the background calibration are compared with the foreground calibration results. The prototype ADC exhibits a DNL of +0.75/$-$0.6 LSB, an INL of +1.77/$-$1.58 LSB, and all spurious components are suppressed to below $-$93 dB when sampled at 5 MHz. The chip occupies an active area of 27 mm$\\sp2,$ and the analog part consumes 60 mW at 5 V. Memory and arithmetic units for calibration are supplied externally in testing.","abstract_has_math":true,"creators":["Kwak, Sung Ung"],"institution":"University of Illinois at Urbana-Champaign","degree_name":"Ph.D.","degree_level":"Dissertation","degree_discipline":"Electrical Engineering","degree_department":null,"school":null,"contributors":["Song, Bang-Sup"],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2015,"date_issued":"2015-09-25T20:10:05Z","date_published":"2015-09-25T20:10:05Z","updated_at":"2026-07-22T22:26:15Z","subjects":["Engineering, Electronics and Electrical"],"languages":["eng"],"rights":[],"rights_urls":[],"identifier_entries":[{"key":"dc:identifier","label":"Identifier","values":["(MiAaPQ)AAI9812665"],"render_values":[{"text":"(MiAaPQ)AAI9812665","href":null,"code":true}]}]},"links":{"outbound_url":"http://hdl.handle.net/2142/81213","outbound_label":"Handle","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Song, Bang-Sup"]},{"key":"dc:creator","label":"Author","values":["Kwak, Sung Ung"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2015-09-25T20:10:05Z","10000-01-01","1997"]},{"key":"dc:type","label":"Dc Type","values":["text"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Electrical Engineering"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Dissertation"]},{"key":"thesis:degree_name","label":"Degree Name","values":["Ph.D."]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["University of Illinois at Urbana-Champaign"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Engineering, Electronics and Electrical"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language","label":"Dc Language","values":["eng"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["http://hdl.handle.net/2142/81213","(MiAaPQ)AAI9812665"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["This thesis presents a 5-5-5-6b pipelined ADC architecture that alleviates the requirements for initial capacitor matching and residue amplifier settling accuracy. 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The two 5-bit MSB stages are digitally calibrated to implement a 15-bit, 5 Msample/s low-spurious ADC using 1.4 $\\mu$m CMOS. A skip-and-fill algorithm with non-linear interpolation also opens up the possibility of calibrating ADCs in the background synchronously with their normal operations. Interpolation results for the background calibration are compared with the foreground calibration results. The prototype ADC exhibits a DNL of +0.75/$-$0.6 LSB, an INL of +1.77/$-$1.58 LSB, and all spurious components are suppressed to below $-$93 dB when sampled at 5 MHz. The chip occupies an active area of 27 mm$\\sp2,$ and the analog part consumes 60 mW at 5 V. Memory and arithmetic units for calibration are supplied externally in testing.","Made available in DSpace on 2015-09-25T20:10:05Z (GMT). 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