{"id":{"repo_id":"uiuc","oai_identifier":"oai:www.ideals.illinois.edu:2142/81154"},"canonical_url":"https://search.dev.ndltd.org/etd/uiuc/oai:www.ideals.illinois.edu:2142/81154","repository":{"repo_id":"uiuc","name":"University of Illinois - Urbana-Champaign","base_url":"https://www.ideals.illinois.edu/oai-pmh"},"display":{"title":"Modeling, Characterization, and Design of Silicon Controlled Rectifiers for Electrostatic Discharge Protection Circuits","abstract":"This dissertation focuses on the characterization, modeling, and design of silicon controlled rectifiers (SCRs) for electrostatic discharge (ESD) protection applications. The oscillatory transmission line pulse (oTLP) measurement is introduced in this work. oTLP measurements enable indirect observation of a device's charge storage duration. When applied to SCRs, this measurement illustrates that trigger voltage is a function of the past state of the device and can be reduced from its quasi-static value by stored charge. Motivated by the device behavior observed with oTLP measurements, a detailed investigation of the SCR's turn-off process is conducted with transmission line pulse (TLP) measurements and device simulations. This investigation reveals that the duration of the turn-off period is a function of well tap connection and well tap spacing. A scalable SCR compact model is developed and implemented in Verilog-A. This model captures the transient effects critical for ESD simulations and the effect of layout spacings on SCR characteristics. The model is extracted and verified in 90 nm and 130 nm technologies. A new dual-base triggered SCR design is presented. This design is shown to have low off-state leakage current, an easily adjustable trigger voltage, and increased immunity to mistriggering.","abstract_html":"This dissertation focuses on the characterization, modeling, and design of silicon controlled rectifiers (SCRs) for electrostatic discharge (ESD) protection applications. The oscillatory transmission line pulse (oTLP) measurement is introduced in this work. oTLP measurements enable indirect observation of a device's charge storage duration. When applied to SCRs, this measurement illustrates that trigger voltage is a function of the past state of the device and can be reduced from its quasi-static value by stored charge. Motivated by the device behavior observed with oTLP measurements, a detailed investigation of the SCR's turn-off process is conducted with transmission line pulse (TLP) measurements and device simulations. This investigation reveals that the duration of the turn-off period is a function of well tap connection and well tap spacing. A scalable SCR compact model is developed and implemented in Verilog-A. This model captures the transient effects critical for ESD simulations and the effect of layout spacings on SCR characteristics. The model is extracted and verified in 90 nm and 130 nm technologies. A new dual-base triggered SCR design is presented. This design is shown to have low off-state leakage current, an easily adjustable trigger voltage, and increased immunity to mistriggering.","abstract_has_math":false,"creators":["Di Sarro, James Paul"],"institution":"University of Illinois at Urbana-Champaign","degree_name":"Ph.D.","degree_level":"Dissertation","degree_discipline":"Electrical and Computer Engineering","degree_department":null,"school":null,"contributors":["Rosenbaum, Elyse"],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2015,"date_issued":"2015-09-25T20:09:47Z","date_published":"2015-09-25T20:09:47Z","updated_at":"2026-07-22T22:26:15Z","subjects":["Engineering, Electronics and Electrical"],"languages":["eng"],"rights":[],"rights_urls":[],"identifier_entries":[{"key":"dc:identifier","label":"Identifier","values":["(MiAaPQ)AAI3399017"],"render_values":[{"text":"(MiAaPQ)AAI3399017","href":null,"code":true}]}]},"links":{"outbound_url":"http://hdl.handle.net/2142/81154","outbound_label":"Handle","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Rosenbaum, Elyse"]},{"key":"dc:creator","label":"Author","values":["Di Sarro, James Paul"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2015-09-25T20:09:47Z","10000-01-01","2009"]},{"key":"dc:type","label":"Dc Type","values":["text"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Electrical and Computer Engineering"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Dissertation"]},{"key":"thesis:degree_name","label":"Degree Name","values":["Ph.D."]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["University of Illinois at Urbana-Champaign"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Engineering, Electronics and Electrical"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language","label":"Dc Language","values":["eng"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["http://hdl.handle.net/2142/81154","(MiAaPQ)AAI3399017"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["This dissertation focuses on the characterization, modeling, and design of silicon controlled rectifiers (SCRs) for electrostatic discharge (ESD) protection applications. The oscillatory transmission line pulse (oTLP) measurement is introduced in this work. oTLP measurements enable indirect observation of a device's charge storage duration. When applied to SCRs, this measurement illustrates that trigger voltage is a function of the past state of the device and can be reduced from its quasi-static value by stored charge. Motivated by the device behavior observed with oTLP measurements, a detailed investigation of the SCR's turn-off process is conducted with transmission line pulse (TLP) measurements and device simulations. This investigation reveals that the duration of the turn-off period is a function of well tap connection and well tap spacing. A scalable SCR compact model is developed and implemented in Verilog-A. This model captures the transient effects critical for ESD simulations and the effect of layout spacings on SCR characteristics. The model is extracted and verified in 90 nm and 130 nm technologies. A new dual-base triggered SCR design is presented. This design is shown to have low off-state leakage current, an easily adjustable trigger voltage, and increased immunity to mistriggering.","Made available in DSpace on 2015-09-25T20:09:47Z (GMT). No. of bitstreams: 2 license.txt: 4848 bytes, checksum: 96035ab3f5e1c23cc7138a224ce498bd (MD5) 3399017.pdf: 1675317 bytes, checksum: 1279a36148703e6a542982abb86aba1c (MD5) Previous issue date: 2009","Embargo set by: Seth Robbins for item 82435 Lift date: Forever Reason: Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs","Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs","U of I Only","116 p.","Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 2009."]},{"key":"dc:title","label":"Title","values":["Modeling, Characterization, and Design of Silicon Controlled Rectifiers for Electrostatic Discharge Protection Circuits"]}]}],"canonical_facts":{"dc:contributor":["Rosenbaum, Elyse"],"dc:creator":["Di Sarro, James Paul"],"dc:date":["2015-09-25T20:09:47Z","10000-01-01","2009"],"dc:description":["This dissertation focuses on the characterization, modeling, and design of silicon controlled rectifiers (SCRs) for electrostatic discharge (ESD) protection applications. The oscillatory transmission line pulse (oTLP) measurement is introduced in this work. oTLP measurements enable indirect observation of a device's charge storage duration. When applied to SCRs, this measurement illustrates that trigger voltage is a function of the past state of the device and can be reduced from its quasi-static value by stored charge. Motivated by the device behavior observed with oTLP measurements, a detailed investigation of the SCR's turn-off process is conducted with transmission line pulse (TLP) measurements and device simulations. This investigation reveals that the duration of the turn-off period is a function of well tap connection and well tap spacing. A scalable SCR compact model is developed and implemented in Verilog-A. This model captures the transient effects critical for ESD simulations and the effect of layout spacings on SCR characteristics. The model is extracted and verified in 90 nm and 130 nm technologies. A new dual-base triggered SCR design is presented. This design is shown to have low off-state leakage current, an easily adjustable trigger voltage, and increased immunity to mistriggering.","Made available in DSpace on 2015-09-25T20:09:47Z (GMT). No. of bitstreams: 2 license.txt: 4848 bytes, checksum: 96035ab3f5e1c23cc7138a224ce498bd (MD5) 3399017.pdf: 1675317 bytes, checksum: 1279a36148703e6a542982abb86aba1c (MD5) Previous issue date: 2009","Embargo set by: Seth Robbins for item 82435 Lift date: Forever Reason: Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs","Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs","U of I Only","116 p.","Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 2009."],"dc:identifier":["http://hdl.handle.net/2142/81154","(MiAaPQ)AAI3399017"],"dc:language":["eng"],"dc:subject":["Engineering, Electronics and Electrical"],"dc:title":["Modeling, Characterization, and Design of Silicon Controlled Rectifiers for Electrostatic Discharge Protection Circuits"],"dc:type":["text"],"thesis:degree_discipline":["Electrical and Computer Engineering"],"thesis:degree_level":["Dissertation"],"thesis:degree_name":["Ph.D."],"thesis:institution_name":["University of Illinois at Urbana-Champaign"]},"updated_at":"2026-07-22T22:26:15Z"}