{"id":{"repo_id":"uiuc","oai_identifier":"oai:www.ideals.illinois.edu:2142/80964"},"canonical_url":"https://search.dev.ndltd.org/etd/uiuc/oai:www.ideals.illinois.edu:2142/80964","repository":{"repo_id":"uiuc","name":"University of Illinois - Urbana-Champaign","base_url":"https://www.ideals.illinois.edu/oai-pmh"},"display":{"title":"Communication-Inspired Design of on -Chip Buses","abstract":"We mitigate the effects of intersymbol interference by employing a variable threshold inverter as an equalizer and operate the bus at rates beyond the rate governed by RC delay of the interconnect. We demonstrate even higher speeds by combining equalization with crosstalk avoidance coding. Simulation results for a 10-mm 32-bit bus in 0.13-mum CMOS technology show that 1.28x speed-up is achievable by equalization alone and 2.30x speed-up is achievable by joint equalization and coding.","abstract_html":"We mitigate the effects of intersymbol interference by employing a variable threshold inverter as an equalizer and operate the bus at rates beyond the rate governed by RC delay of the interconnect. We demonstrate even higher speeds by combining equalization with crosstalk avoidance coding. Simulation results for a 10-mm 32-bit bus in 0.13-mum CMOS technology show that 1.28x speed-up is achievable by equalization alone and 2.30x speed-up is achievable by joint equalization and coding.","abstract_has_math":false,"creators":["Sridhara, Srinivasa Raghavan"],"institution":"University of Illinois at Urbana-Champaign","degree_name":"Ph.D.","degree_level":"Dissertation","degree_discipline":"Electrical Engineering","degree_department":null,"school":null,"contributors":["Shanbhag, Naresh R."],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2015,"date_issued":"2015-09-25T20:09:01Z","date_published":"2015-09-25T20:09:01Z","updated_at":"2026-07-22T22:26:15Z","subjects":["Engineering, Electronics and Electrical"],"languages":["eng"],"rights":[],"rights_urls":[],"identifier_entries":[{"key":"dc:identifier","label":"Identifier","values":["(MiAaPQ)AAI3223723"],"render_values":[{"text":"(MiAaPQ)AAI3223723","href":null,"code":true}]}]},"links":{"outbound_url":"http://hdl.handle.net/2142/80964","outbound_label":"Handle","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Shanbhag, Naresh R."]},{"key":"dc:creator","label":"Author","values":["Sridhara, Srinivasa Raghavan"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2015-09-25T20:09:01Z","10000-01-01","2006"]},{"key":"dc:type","label":"Dc Type","values":["text"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Electrical Engineering"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Dissertation"]},{"key":"thesis:degree_name","label":"Degree Name","values":["Ph.D."]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["University of Illinois at Urbana-Champaign"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Engineering, Electronics and Electrical"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language","label":"Dc Language","values":["eng"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["http://hdl.handle.net/2142/80964","(MiAaPQ)AAI3223723"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["We mitigate the effects of intersymbol interference by employing a variable threshold inverter as an equalizer and operate the bus at rates beyond the rate governed by RC delay of the interconnect. We demonstrate even higher speeds by combining equalization with crosstalk avoidance coding. Simulation results for a 10-mm 32-bit bus in 0.13-mum CMOS technology show that 1.28x speed-up is achievable by equalization alone and 2.30x speed-up is achievable by joint equalization and coding.","Made available in DSpace on 2015-09-25T20:09:01Z (GMT). No. of bitstreams: 2 license.txt: 4848 bytes, checksum: 96035ab3f5e1c23cc7138a224ce498bd (MD5) 3223723.pdf: 2924297 bytes, checksum: 3aa2147783e285547539af110d19b0c8 (MD5) Previous issue date: 2006","Embargo set by: Seth Robbins for item 82246 Lift date: Forever Reason: Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs","Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs","U of I Only","102 p.","Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 2006."]},{"key":"dc:title","label":"Title","values":["Communication-Inspired Design of on -Chip Buses"]}]}],"canonical_facts":{"dc:contributor":["Shanbhag, Naresh R."],"dc:creator":["Sridhara, Srinivasa Raghavan"],"dc:date":["2015-09-25T20:09:01Z","10000-01-01","2006"],"dc:description":["We mitigate the effects of intersymbol interference by employing a variable threshold inverter as an equalizer and operate the bus at rates beyond the rate governed by RC delay of the interconnect. We demonstrate even higher speeds by combining equalization with crosstalk avoidance coding. Simulation results for a 10-mm 32-bit bus in 0.13-mum CMOS technology show that 1.28x speed-up is achievable by equalization alone and 2.30x speed-up is achievable by joint equalization and coding.","Made available in DSpace on 2015-09-25T20:09:01Z (GMT). No. of bitstreams: 2 license.txt: 4848 bytes, checksum: 96035ab3f5e1c23cc7138a224ce498bd (MD5) 3223723.pdf: 2924297 bytes, checksum: 3aa2147783e285547539af110d19b0c8 (MD5) Previous issue date: 2006","Embargo set by: Seth Robbins for item 82246 Lift date: Forever Reason: Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs","Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs","U of I Only","102 p.","Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 2006."],"dc:identifier":["http://hdl.handle.net/2142/80964","(MiAaPQ)AAI3223723"],"dc:language":["eng"],"dc:subject":["Engineering, Electronics and Electrical"],"dc:title":["Communication-Inspired Design of on -Chip Buses"],"dc:type":["text"],"thesis:degree_discipline":["Electrical Engineering"],"thesis:degree_level":["Dissertation"],"thesis:degree_name":["Ph.D."],"thesis:institution_name":["University of Illinois at Urbana-Champaign"]},"updated_at":"2026-07-22T22:26:15Z"}