{"id":{"repo_id":"uiuc","oai_identifier":"oai:www.ideals.illinois.edu:2142/80944"},"canonical_url":"https://search.dev.ndltd.org/etd/uiuc/oai:www.ideals.illinois.edu:2142/80944","repository":{"repo_id":"uiuc","name":"University of Illinois - Urbana-Champaign","base_url":"https://www.ideals.illinois.edu/oai-pmh"},"display":{"title":"Dynamic Optimization in Hardware","abstract":"On a broad level, we describe the relationship between well-known compiler optimization concepts and hardware-implemented optimizations. We define and explore two hardware-centric dynamic optimization paradigms: continuous optimization and discrete optimization. Continuous optimization optimizes instructions in the processor pipeline prior to execution. It is primarily useful for reducing processor resource contention and increasing ILP. Discrete optimization captures reusable chunks of the dynamic instruction stream, optimizes them, and then sequences them back into execution. Its primary benefits come from reducing instruction count and increasing ILP. The benefits of these two models are mostly orthogonal, and, therefore, they can be combined to provide larger improvements than either approach could provide by itself.","abstract_html":"On a broad level, we describe the relationship between well-known compiler optimization concepts and hardware-implemented optimizations. We define and explore two hardware-centric dynamic optimization paradigms: continuous optimization and discrete optimization. Continuous optimization optimizes instructions in the processor pipeline prior to execution. It is primarily useful for reducing processor resource contention and increasing ILP. Discrete optimization captures reusable chunks of the dynamic instruction stream, optimizes them, and then sequences them back into execution. Its primary benefits come from reducing instruction count and increasing ILP. The benefits of these two models are mostly orthogonal, and, therefore, they can be combined to provide larger improvements than either approach could provide by itself.","abstract_has_math":false,"creators":["Fahs, Brian Matthew"],"institution":"University of Illinois at Urbana-Champaign","degree_name":"Ph.D.","degree_level":"Dissertation","degree_discipline":"Electrical Engineering","degree_department":null,"school":null,"contributors":["Patel, Sanjay J.","Lumetta, Steven S."],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2015,"date_issued":"2015-09-25T20:08:57Z","date_published":"2015-09-25T20:08:57Z","updated_at":"2026-07-22T22:26:15Z","subjects":["Computer Science"],"languages":["eng"],"rights":[],"rights_urls":[],"identifier_entries":[{"key":"dc:identifier","label":"Identifier","values":["(MiAaPQ)AAI3202089"],"render_values":[{"text":"(MiAaPQ)AAI3202089","href":null,"code":true}]}]},"links":{"outbound_url":"http://hdl.handle.net/2142/80944","outbound_label":"Handle","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Patel, Sanjay J.","Lumetta, Steven S."]},{"key":"dc:creator","label":"Author","values":["Fahs, Brian Matthew"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2015-09-25T20:08:57Z","10000-01-01","2005"]},{"key":"dc:type","label":"Dc Type","values":["text"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Electrical Engineering"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Dissertation"]},{"key":"thesis:degree_name","label":"Degree Name","values":["Ph.D."]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["University of Illinois at Urbana-Champaign"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Computer Science"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language","label":"Dc Language","values":["eng"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["http://hdl.handle.net/2142/80944","(MiAaPQ)AAI3202089"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["On a broad level, we describe the relationship between well-known compiler optimization concepts and hardware-implemented optimizations. We define and explore two hardware-centric dynamic optimization paradigms: continuous optimization and discrete optimization. Continuous optimization optimizes instructions in the processor pipeline prior to execution. It is primarily useful for reducing processor resource contention and increasing ILP. Discrete optimization captures reusable chunks of the dynamic instruction stream, optimizes them, and then sequences them back into execution. Its primary benefits come from reducing instruction count and increasing ILP. The benefits of these two models are mostly orthogonal, and, therefore, they can be combined to provide larger improvements than either approach could provide by itself.","Made available in DSpace on 2015-09-25T20:08:57Z (GMT). No. of bitstreams: 2 license.txt: 4848 bytes, checksum: 96035ab3f5e1c23cc7138a224ce498bd (MD5) 3202089.pdf: 6882996 bytes, checksum: 5d5b518b97c6c2772982b619e2117eb4 (MD5) Previous issue date: 2005","Embargo set by: Seth Robbins for item 82226 Lift date: Forever Reason: Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs","Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs","U of I Only","229 p.","Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 2005."]},{"key":"dc:title","label":"Title","values":["Dynamic Optimization in Hardware"]}]}],"canonical_facts":{"dc:contributor":["Patel, Sanjay J.","Lumetta, Steven S."],"dc:creator":["Fahs, Brian Matthew"],"dc:date":["2015-09-25T20:08:57Z","10000-01-01","2005"],"dc:description":["On a broad level, we describe the relationship between well-known compiler optimization concepts and hardware-implemented optimizations. We define and explore two hardware-centric dynamic optimization paradigms: continuous optimization and discrete optimization. Continuous optimization optimizes instructions in the processor pipeline prior to execution. It is primarily useful for reducing processor resource contention and increasing ILP. Discrete optimization captures reusable chunks of the dynamic instruction stream, optimizes them, and then sequences them back into execution. Its primary benefits come from reducing instruction count and increasing ILP. The benefits of these two models are mostly orthogonal, and, therefore, they can be combined to provide larger improvements than either approach could provide by itself.","Made available in DSpace on 2015-09-25T20:08:57Z (GMT). No. of bitstreams: 2 license.txt: 4848 bytes, checksum: 96035ab3f5e1c23cc7138a224ce498bd (MD5) 3202089.pdf: 6882996 bytes, checksum: 5d5b518b97c6c2772982b619e2117eb4 (MD5) Previous issue date: 2005","Embargo set by: Seth Robbins for item 82226 Lift date: Forever Reason: Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs","Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs","U of I Only","229 p.","Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 2005."],"dc:identifier":["http://hdl.handle.net/2142/80944","(MiAaPQ)AAI3202089"],"dc:language":["eng"],"dc:subject":["Computer Science"],"dc:title":["Dynamic Optimization in Hardware"],"dc:type":["text"],"thesis:degree_discipline":["Electrical Engineering"],"thesis:degree_level":["Dissertation"],"thesis:degree_name":["Ph.D."],"thesis:institution_name":["University of Illinois at Urbana-Champaign"]},"updated_at":"2026-07-22T22:26:15Z"}