{"id":{"repo_id":"uiuc","oai_identifier":"oai:www.ideals.illinois.edu:2142/80900"},"canonical_url":"https://search.dev.ndltd.org/etd/uiuc/oai:www.ideals.illinois.edu:2142/80900","repository":{"repo_id":"uiuc","name":"University of Illinois - Urbana-Champaign","base_url":"https://www.ideals.illinois.edu/oai-pmh"},"display":{"title":"Multiple-Pass Pipelining: Enhancing in-Order Microarchitectures to Out-of-Order Performance","abstract":"\"With two-pass pipelining, programs execute on two in-order back-end pipelines coupled by a queue. The \"\"advance\"\" pipeline often defers instructions dispatching with unready operands rather than stalling. The \"\"backup\"\" pipeline allows concurrent resolution of instructions deferred by the first pipeline allowing overlapping of useful \"\"advanced\"\" execution with miss resolution. Multipass pipelining is based upon a similar concept, but overcomes the shortfalls of two-pass pipelining through simultaneous execution of architectural and advance instructions on a common pipeline in a simultaneous multithreading-like fashion. These techniques perform similarly to achievable out-of-order designs while comparing favorably in terms of power and complexity. An accompanying compiler technique and instruction marking further enhances the handling of miss latencies and reduces fruitless speculative execution by statically denoting instructions that, when stalled, indicate there is little opportunity for advanced execution.\"","abstract_html":""With two-pass pipelining, programs execute on two in-order back-end pipelines coupled by a queue. The ""advance"" pipeline often defers instructions dispatching with unready operands rather than stalling. The ""backup"" pipeline allows concurrent resolution of instructions deferred by the first pipeline allowing overlapping of useful ""advanced"" execution with miss resolution. Multipass pipelining is based upon a similar concept, but overcomes the shortfalls of two-pass pipelining through simultaneous execution of architectural and advance instructions on a common pipeline in a simultaneous multithreading-like fashion. These techniques perform similarly to achievable out-of-order designs while comparing favorably in terms of power and complexity. An accompanying compiler technique and instruction marking further enhances the handling of miss latencies and reduces fruitless speculative execution by statically denoting instructions that, when stalled, indicate there is little opportunity for advanced execution."","abstract_has_math":false,"creators":["Barnes, Ronald D., Jr"],"institution":"University of Illinois at Urbana-Champaign","degree_name":"Ph.D.","degree_level":"Dissertation","degree_discipline":"Electrical Engineering","degree_department":null,"school":null,"contributors":["Hwu, Wen-Mei W."],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2015,"date_issued":"2015-09-25T20:08:44Z","date_published":"2015-09-25T20:08:44Z","updated_at":"2026-07-22T22:26:15Z","subjects":["Engineering, Electronics and Electrical"],"languages":["eng"],"rights":[],"rights_urls":[],"identifier_entries":[{"key":"dc:identifier","label":"Identifier","values":["(MiAaPQ)AAI3182218"],"render_values":[{"text":"(MiAaPQ)AAI3182218","href":null,"code":true}]}]},"links":{"outbound_url":"http://hdl.handle.net/2142/80900","outbound_label":"Handle","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Hwu, Wen-Mei W."]},{"key":"dc:creator","label":"Author","values":["Barnes, Ronald D., Jr"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2015-09-25T20:08:44Z","10000-01-01","2005"]},{"key":"dc:type","label":"Dc Type","values":["text"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Electrical Engineering"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Dissertation"]},{"key":"thesis:degree_name","label":"Degree Name","values":["Ph.D."]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["University of Illinois at Urbana-Champaign"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Engineering, Electronics and Electrical"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language","label":"Dc Language","values":["eng"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["http://hdl.handle.net/2142/80900","(MiAaPQ)AAI3182218"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["\"With two-pass pipelining, programs execute on two in-order back-end pipelines coupled by a queue. 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The \"\"advance\"\" pipeline often defers instructions dispatching with unready operands rather than stalling. The \"\"backup\"\" pipeline allows concurrent resolution of instructions deferred by the first pipeline allowing overlapping of useful \"\"advanced\"\" execution with miss resolution. Multipass pipelining is based upon a similar concept, but overcomes the shortfalls of two-pass pipelining through simultaneous execution of architectural and advance instructions on a common pipeline in a simultaneous multithreading-like fashion. These techniques perform similarly to achievable out-of-order designs while comparing favorably in terms of power and complexity. An accompanying compiler technique and instruction marking further enhances the handling of miss latencies and reduces fruitless speculative execution by statically denoting instructions that, when stalled, indicate there is little opportunity for advanced execution.\"","Made available in DSpace on 2015-09-25T20:08:44Z (GMT). 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