{"id":{"repo_id":"uiuc","oai_identifier":"oai:www.ideals.illinois.edu:2142/80760"},"canonical_url":"https://search.dev.ndltd.org/etd/uiuc/oai:www.ideals.illinois.edu:2142/80760","repository":{"repo_id":"uiuc","name":"University of Illinois - Urbana-Champaign","base_url":"https://www.ideals.illinois.edu/oai-pmh"},"display":{"title":"Nanothreads: Flexible Thread Scheduling","abstract":"The impacts of a shared arena architecture for scheduling threads is analyzed with legacy applications such as FORTRAN computational chemical simulations and mathematical solvers that consume significant processing time in large systems and are difficult to redesign. A representative set of applications from the NAS benchmarks had only their runtime replaced with a new runtime that makes use of the shared arena in IRIX 6.5, and were found to improve their execution time over 14 times when there was a single process used in a 16 processor Origin 2000 from Silicon Graphics, Inc. Another implementation in Linux 2.4 was used to test context-switch performance amongst comparable thread models. Though, the nanoThread scheduler interface is more complicated than the comparable threading designs presented, the performance improvements shown in this dissertation prove that this more efficient thread model warrants implementation in commercial operating systems.","abstract_html":"The impacts of a shared arena architecture for scheduling threads is analyzed with legacy applications such as FORTRAN computational chemical simulations and mathematical solvers that consume significant processing time in large systems and are difficult to redesign. A representative set of applications from the NAS benchmarks had only their runtime replaced with a new runtime that makes use of the shared arena in IRIX 6.5, and were found to improve their execution time over 14 times when there was a single process used in a 16 processor Origin 2000 from Silicon Graphics, Inc. Another implementation in Linux 2.4 was used to test context-switch performance amongst comparable thread models. Though, the nanoThread scheduler interface is more complicated than the comparable threading designs presented, the performance improvements shown in this dissertation prove that this more efficient thread model warrants implementation in commercial operating systems.","abstract_has_math":false,"creators":["Craig, David William"],"institution":"University of Illinois at Urbana-Champaign","degree_name":"Ph.D.","degree_level":"Dissertation","degree_discipline":"Electrical Engineering","degree_department":null,"school":null,"contributors":["Polychronopoulos, Constantine D."],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2015,"date_issued":"2015-09-25T20:08:02Z","date_published":"2015-09-25T20:08:02Z","updated_at":"2026-07-22T22:26:14Z","subjects":["Engineering, Electronics and Electrical"],"languages":["eng"],"rights":[],"rights_urls":[],"identifier_entries":[{"key":"dc:identifier","label":"Identifier","values":["(MiAaPQ)AAI3044076"],"render_values":[{"text":"(MiAaPQ)AAI3044076","href":null,"code":true}]}]},"links":{"outbound_url":"http://hdl.handle.net/2142/80760","outbound_label":"Handle","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Polychronopoulos, Constantine D."]},{"key":"dc:creator","label":"Author","values":["Craig, David William"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2015-09-25T20:08:02Z","10000-01-01","2002"]},{"key":"dc:type","label":"Dc Type","values":["text"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Electrical Engineering"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Dissertation"]},{"key":"thesis:degree_name","label":"Degree Name","values":["Ph.D."]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["University of Illinois at Urbana-Champaign"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Engineering, Electronics and Electrical"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language","label":"Dc Language","values":["eng"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["http://hdl.handle.net/2142/80760","(MiAaPQ)AAI3044076"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["The impacts of a shared arena architecture for scheduling threads is analyzed with legacy applications such as FORTRAN computational chemical simulations and mathematical solvers that consume significant processing time in large systems and are difficult to redesign. A representative set of applications from the NAS benchmarks had only their runtime replaced with a new runtime that makes use of the shared arena in IRIX 6.5, and were found to improve their execution time over 14 times when there was a single process used in a 16 processor Origin 2000 from Silicon Graphics, Inc. Another implementation in Linux 2.4 was used to test context-switch performance amongst comparable thread models. Though, the nanoThread scheduler interface is more complicated than the comparable threading designs presented, the performance improvements shown in this dissertation prove that this more efficient thread model warrants implementation in commercial operating systems.","Made available in DSpace on 2015-09-25T20:08:02Z (GMT). No. of bitstreams: 2 license.txt: 4848 bytes, checksum: 96035ab3f5e1c23cc7138a224ce498bd (MD5) 3044076.pdf: 7579700 bytes, checksum: 03e8267f319011bbbdd6faf8b5f43a01 (MD5) Previous issue date: 2002","Embargo set by: Seth Robbins for item 82042 Lift date: Forever Reason: Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs","Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs","U of I Only","133 p.","Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 2002."]},{"key":"dc:title","label":"Title","values":["Nanothreads: Flexible Thread Scheduling"]}]}],"canonical_facts":{"dc:contributor":["Polychronopoulos, Constantine D."],"dc:creator":["Craig, David William"],"dc:date":["2015-09-25T20:08:02Z","10000-01-01","2002"],"dc:description":["The impacts of a shared arena architecture for scheduling threads is analyzed with legacy applications such as FORTRAN computational chemical simulations and mathematical solvers that consume significant processing time in large systems and are difficult to redesign. A representative set of applications from the NAS benchmarks had only their runtime replaced with a new runtime that makes use of the shared arena in IRIX 6.5, and were found to improve their execution time over 14 times when there was a single process used in a 16 processor Origin 2000 from Silicon Graphics, Inc. Another implementation in Linux 2.4 was used to test context-switch performance amongst comparable thread models. Though, the nanoThread scheduler interface is more complicated than the comparable threading designs presented, the performance improvements shown in this dissertation prove that this more efficient thread model warrants implementation in commercial operating systems.","Made available in DSpace on 2015-09-25T20:08:02Z (GMT). No. of bitstreams: 2 license.txt: 4848 bytes, checksum: 96035ab3f5e1c23cc7138a224ce498bd (MD5) 3044076.pdf: 7579700 bytes, checksum: 03e8267f319011bbbdd6faf8b5f43a01 (MD5) Previous issue date: 2002","Embargo set by: Seth Robbins for item 82042 Lift date: Forever Reason: Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs","Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs","U of I Only","133 p.","Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 2002."],"dc:identifier":["http://hdl.handle.net/2142/80760","(MiAaPQ)AAI3044076"],"dc:language":["eng"],"dc:subject":["Engineering, Electronics and Electrical"],"dc:title":["Nanothreads: Flexible Thread Scheduling"],"dc:type":["text"],"thesis:degree_discipline":["Electrical Engineering"],"thesis:degree_level":["Dissertation"],"thesis:degree_name":["Ph.D."],"thesis:institution_name":["University of Illinois at Urbana-Champaign"]},"updated_at":"2026-07-22T22:26:14Z"}