{"id":{"repo_id":"uiuc","oai_identifier":"oai:www.ideals.illinois.edu:2142/80704"},"canonical_url":"https://search.dev.ndltd.org/etd/uiuc/oai:www.ideals.illinois.edu:2142/80704","repository":{"repo_id":"uiuc","name":"University of Illinois - Urbana-Champaign","base_url":"https://www.ideals.illinois.edu/oai-pmh"},"display":{"title":"High-Resolution Nyquist -Rate Analog -to -Digital Converter","abstract":"This thesis presents a pipelined analog-to-digital converter (ADC) employing a capacitor error-averaging technique with look-ahead decision and digital error correction concepts that has been implemented in a CMOS technology to achieve high linearity and high speed. The capacitor error-averaging technique can perform an accurate multiply-by-two (x2) function required in high-resolution pipelined ADCs, while a high gain op-amp has been designed to minimize error due to finite DC gain. Three clock phases are required by the capacitor error-averaging technique (rather than the conventional two clock phases), and the look-ahead decision technique takes advantage of this by allowing the residue amplifiers a full clock phase of settling time (rather than a partial clock phase in a conventional pipelined ADC). The fully differential pipelined ADC achieves a throughput rate of 20 Msamples/s and a linearity of 14 b without any type of trimming or calibration. The prototype ADC, fabricated in a double-poly triple-metal 0.5-mum CMOS process, exhibits a differential nonlinearity (DNL) of +0.23/-0.28 least significant bit (LSB), an integral nonlinearity (INL) of +0.95/-1.06 LSB, a spurious-free dynamic range (SFDR) of 91.6 dB, and a signal-to-noise ratio (SNR) of 74.2 dB with a 1-MHz input and a 20-MHz clock. The chip occupies an active area of 10.8 mm 2 including digital logic, output buffers, and bond pads, and consumes 720 mW at 5 V.","abstract_html":"This thesis presents a pipelined analog-to-digital converter (ADC) employing a capacitor error-averaging technique with look-ahead decision and digital error correction concepts that has been implemented in a CMOS technology to achieve high linearity and high speed. The capacitor error-averaging technique can perform an accurate multiply-by-two (x2) function required in high-resolution pipelined ADCs, while a high gain op-amp has been designed to minimize error due to finite DC gain. Three clock phases are required by the capacitor error-averaging technique (rather than the conventional two clock phases), and the look-ahead decision technique takes advantage of this by allowing the residue amplifiers a full clock phase of settling time (rather than a partial clock phase in a conventional pipelined ADC). The fully differential pipelined ADC achieves a throughput rate of 20 Msamples/s and a linearity of 14 b without any type of trimming or calibration. The prototype ADC, fabricated in a double-poly triple-metal 0.5-mum CMOS process, exhibits a differential nonlinearity (DNL) of +0.23/-0.28 least significant bit (LSB), an integral nonlinearity (INL) of +0.95/-1.06 LSB, a spurious-free dynamic range (SFDR) of 91.6 dB, and a signal-to-noise ratio (SNR) of 74.2 dB with a 1-MHz input and a 20-MHz clock. The chip occupies an active area of 10.8 mm 2 including digital logic, output buffers, and bond pads, and consumes 720 mW at 5 V.","abstract_has_math":false,"creators":["Chen, Hsin-Shu"],"institution":"University of Illinois at Urbana-Champaign","degree_name":"Ph.D.","degree_level":"Dissertation","degree_discipline":"Electrical Engineering","degree_department":null,"school":null,"contributors":["Song, Bang-Sup"],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2015,"date_issued":"2015-09-25T20:07:43Z","date_published":"2015-09-25T20:07:43Z","updated_at":"2026-07-22T22:26:14Z","subjects":["Engineering, Electronics and Electrical"],"languages":["eng"],"rights":[],"rights_urls":[],"identifier_entries":[{"key":"dc:identifier","label":"Identifier","values":["(MiAaPQ)AAI3017039"],"render_values":[{"text":"(MiAaPQ)AAI3017039","href":null,"code":true}]}]},"links":{"outbound_url":"http://hdl.handle.net/2142/80704","outbound_label":"Handle","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Song, Bang-Sup"]},{"key":"dc:creator","label":"Author","values":["Chen, Hsin-Shu"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2015-09-25T20:07:43Z","10000-01-01","2001"]},{"key":"dc:type","label":"Dc Type","values":["text"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Electrical Engineering"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Dissertation"]},{"key":"thesis:degree_name","label":"Degree Name","values":["Ph.D."]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["University of Illinois at Urbana-Champaign"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Engineering, Electronics and Electrical"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language","label":"Dc Language","values":["eng"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["http://hdl.handle.net/2142/80704","(MiAaPQ)AAI3017039"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["This thesis presents a pipelined analog-to-digital converter (ADC) employing a capacitor error-averaging technique with look-ahead decision and digital error correction concepts that has been implemented in a CMOS technology to achieve high linearity and high speed. The capacitor error-averaging technique can perform an accurate multiply-by-two (x2) function required in high-resolution pipelined ADCs, while a high gain op-amp has been designed to minimize error due to finite DC gain. Three clock phases are required by the capacitor error-averaging technique (rather than the conventional two clock phases), and the look-ahead decision technique takes advantage of this by allowing the residue amplifiers a full clock phase of settling time (rather than a partial clock phase in a conventional pipelined ADC). The fully differential pipelined ADC achieves a throughput rate of 20 Msamples/s and a linearity of 14 b without any type of trimming or calibration. The prototype ADC, fabricated in a double-poly triple-metal 0.5-mum CMOS process, exhibits a differential nonlinearity (DNL) of +0.23/-0.28 least significant bit (LSB), an integral nonlinearity (INL) of +0.95/-1.06 LSB, a spurious-free dynamic range (SFDR) of 91.6 dB, and a signal-to-noise ratio (SNR) of 74.2 dB with a 1-MHz input and a 20-MHz clock. The chip occupies an active area of 10.8 mm 2 including digital logic, output buffers, and bond pads, and consumes 720 mW at 5 V.","Made available in DSpace on 2015-09-25T20:07:43Z (GMT). No. of bitstreams: 2 license.txt: 4848 bytes, checksum: 96035ab3f5e1c23cc7138a224ce498bd (MD5) 3017039.pdf: 4235287 bytes, checksum: d884bb50149923182951bd32abf0aa1e (MD5) Previous issue date: 2001","Embargo set by: Seth Robbins for item 81986 Lift date: Forever Reason: Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs","Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs","U of I Only","118 p.","Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 2001."]},{"key":"dc:title","label":"Title","values":["High-Resolution Nyquist -Rate Analog -to -Digital Converter"]}]}],"canonical_facts":{"dc:contributor":["Song, Bang-Sup"],"dc:creator":["Chen, Hsin-Shu"],"dc:date":["2015-09-25T20:07:43Z","10000-01-01","2001"],"dc:description":["This thesis presents a pipelined analog-to-digital converter (ADC) employing a capacitor error-averaging technique with look-ahead decision and digital error correction concepts that has been implemented in a CMOS technology to achieve high linearity and high speed. The capacitor error-averaging technique can perform an accurate multiply-by-two (x2) function required in high-resolution pipelined ADCs, while a high gain op-amp has been designed to minimize error due to finite DC gain. Three clock phases are required by the capacitor error-averaging technique (rather than the conventional two clock phases), and the look-ahead decision technique takes advantage of this by allowing the residue amplifiers a full clock phase of settling time (rather than a partial clock phase in a conventional pipelined ADC). The fully differential pipelined ADC achieves a throughput rate of 20 Msamples/s and a linearity of 14 b without any type of trimming or calibration. The prototype ADC, fabricated in a double-poly triple-metal 0.5-mum CMOS process, exhibits a differential nonlinearity (DNL) of +0.23/-0.28 least significant bit (LSB), an integral nonlinearity (INL) of +0.95/-1.06 LSB, a spurious-free dynamic range (SFDR) of 91.6 dB, and a signal-to-noise ratio (SNR) of 74.2 dB with a 1-MHz input and a 20-MHz clock. The chip occupies an active area of 10.8 mm 2 including digital logic, output buffers, and bond pads, and consumes 720 mW at 5 V.","Made available in DSpace on 2015-09-25T20:07:43Z (GMT). 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