Refresh reduction in dynamic memories
type: CreativeWork
description: An effective approach to reduce the static energy consumption of large on-chip memories is to use a low-leakage technology such as embedded DRAM (eDRAM). Unfortunately, eDRAM, being a dynamic memory, requires periodic refresh, which ends up consuming substantial energy for large last-level caches. In upcoming architectures that stack a processor die and multiple DRAM dies, DRAM dies experience higher temperatures. Elevated temperatures increase the periodic refresh requirement of DRAM, also a dynamic memory, which increases its energy and hurts processor performance. In this thesis, we propose and evaluate techniques for refresh reduction in dynamic memories. We examine the opportunity of refreshing only the data that will be used in the near future and only if the data has not been recently accessed (and automatically refreshed). We present Refrint, a simple approach to perform fine-grained refresh of on-chip eDRAM multiprocessor cache hierarchies. We show that an eDRAM-based memory hierarchy with Refrint consumes only 30% of the energy of a conventional SRAM-based memory hierarchy, and induces a slowdown of only 6%. In contrast, an eDRAM-based memory hierarchy without Refrint consumes 56% of the energy of the conventional memory hierarchy, inducing a slowdown of 25%. While it is well known that different eDRAM cells exhibit very different charge-retention properties, current systems pessimistically assume worst-case retention times, and refresh all the cells at a conservatively-high rate. We use known facts about the factors that determine the retention properties of cells to build a new model of eDRAM retention times. The model is called Mosaic. We show that the retention times of cells in large eDRAM modules exhibit substantial spatial correlation. We propose a mechanism to exploit such correlation to save refresh energy. With simple techniques, we reduce the refresh energy of large eDRAM modules by 20x. The result is that refresh energy is all but eliminated. F…
abstract: An effective approach to reduce the static energy consumption of large on-chip memories is to use a low-leakage technology such as embedded DRAM (eDRAM). Unfortunately, eDRAM, being a dynamic memory, requires periodic refresh, which ends up consuming substantial energy for large last-level caches. In upcoming architectures that stack a processor die and multiple DRAM dies, DRAM dies experience higher temperatures. Elevated temperatures increase the periodic refresh requirement of DRAM, also a dynamic memory, which increases its energy and hurts processor performance. In this thesis, we propose and evaluate techniques for refresh reduction in dynamic memories. We examine the opportunity of refreshing only the data that will be used in the near future and only if the data has not been recently accessed (and automatically refreshed). We present Refrint, a simple approach to perform fine-grained refresh of on-chip eDRAM multiprocessor cache hierarchies. We show that an eDRAM-based memory hierarchy with Refrint consumes only 30% of the energy of a conventional SRAM-based memory hierarchy, and induces a slowdown of only 6%. In contrast, an eDRAM-based memory hierarchy without Refrint consumes 56% of the energy of the conventional memory hierarchy, inducing a slowdown of 25%. While it is well known that different eDRAM cells exhibit very different charge-retention properties, current systems pessimistically assume worst-case retention times, and refresh all the cells at a conservatively-high rate. We use known facts about the factors that determine the retention properties of cells to build a new model of eDRAM retention times. The model is called Mosaic. We show that the retention times of cells in large eDRAM modules exhibit substantial spatial correlation. We propose a mechanism to exploit such correlation to save refresh energy. With simple techniques, we reduce the refresh energy of large eDRAM modules by 20x. The result is that refresh energy is all but eliminated. F…
author: Agrawal, Aditya
language: en
keywords: dynamic random-access memory (DRAM), embedded dynamic random-access memory (eDRAM), Cache, dynamic memory, refresh, three-dimensional (3D), stacking, retention time, Through Silicon Vias (TSV), Thermal Through Silicon Vias (TTSV), temperature, leakage, variation, spatial
date published: 2015-01-21T19:55:05Z
date modified: 2026-07-22T22:26:07Z
provider: University of Illinois - Urbana-Champaign
publisher: Networked Digital Library of Theses and Dissertations
type: WebPage
source organization: University of Illinois at Urbana-Champaign

PropertyValue
property ID: Handle
value: http://hdl.handle.net/2142/72970