{"id":{"repo_id":"uiuc","oai_identifier":"oai:www.ideals.illinois.edu:2142/72024"},"canonical_url":"https://search.dev.ndltd.org/etd/uiuc/oai:www.ideals.illinois.edu:2142/72024","repository":{"repo_id":"uiuc","name":"University of Illinois - Urbana-Champaign","base_url":"https://www.ideals.illinois.edu/oai-pmh"},"display":{"title":"Physical Design for Multichip Modules","abstract":"This thesis deals with four physical design problems in the multichip module (MCM) environment: interconnect analysis, chip placement, global tree construction, and layer assignment. The emphasis is on maximizing the electrical performance, based on accurate modeling of MCM interconnect behavior. A new approach, called Reciprocal Expansion, is developed for rapidly estimating the time-domain response of lossy coupled MCM interconnect structures, and its accuracy and efficiency are demonstrated experimentally. A second-order RLC delay model is presented, which captures the effects of line resistance and inductance on signal delay. A "resistance-driven" chip placement algorithm is described, which takes interconnect resistance into account to find a placement with minimum net delays. Multilayer MCM routing is decomposed into two stages: two-dimensional global tree construction and layer assignment. An algorithm for global tree construction is presented, which attempts to minimize the number and length of stubs, while simultaneously minimizing the second-order delay. Finally, the layer assignment problem is considered. A model for the multilayer ceramic MCM environment is developed. Theoretical results on the complexity of the layer assignment problem on this model are derived, and an effective heuristic algorithm is presented. A second approach to layer assignment, based on max-cut partitioning of a net interference graph, is also studied. New techniques for constructing the interference graph based on congestion and crosstalk are presented, and algorithms for max-cut partitioning and crosstalk minimization are described.","abstract_html":"This thesis deals with four physical design problems in the multichip module (MCM) environment: interconnect analysis, chip placement, global tree construction, and layer assignment. The emphasis is on maximizing the electrical performance, based on accurate modeling of MCM interconnect behavior. A new approach, called Reciprocal Expansion, is developed for rapidly estimating the time-domain response of lossy coupled MCM interconnect structures, and its accuracy and efficiency are demonstrated experimentally. A second-order RLC delay model is presented, which captures the effects of line resistance and inductance on signal delay. A "resistance-driven" chip placement algorithm is described, which takes interconnect resistance into account to find a placement with minimum net delays. Multilayer MCM routing is decomposed into two stages: two-dimensional global tree construction and layer assignment. An algorithm for global tree construction is presented, which attempts to minimize the number and length of stubs, while simultaneously minimizing the second-order delay. Finally, the layer assignment problem is considered. A model for the multilayer ceramic MCM environment is developed. Theoretical results on the complexity of the layer assignment problem on this model are derived, and an effective heuristic algorithm is presented. A second approach to layer assignment, based on max-cut partitioning of a net interference graph, is also studied. New techniques for constructing the interference graph based on congestion and crosstalk are presented, and algorithms for max-cut partitioning and crosstalk minimization are described.","abstract_has_math":false,"creators":["Sriram, M."],"institution":"University of Illinois at Urbana-Champaign","degree_name":"Ph.D.","degree_level":"Dissertation","degree_discipline":"Electrical Engineering","degree_department":null,"school":null,"contributors":["Kang, S.M."],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2014,"date_issued":"2014-12-16T22:23:24Z","date_published":"2014-12-16T22:23:24Z","updated_at":"2026-07-22T22:26:06Z","subjects":["Engineering, Electronics and Electrical"],"languages":[],"rights":[],"rights_urls":[],"identifier_entries":[{"key":"dc:identifier","label":"Identifier","values":["(UMI)AAI9411790"],"render_values":[{"text":"(UMI)AAI9411790","href":null,"code":true}]}]},"links":{"outbound_url":"http://hdl.handle.net/2142/72024","outbound_label":"Handle","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Kang, S.M."]},{"key":"dc:creator","label":"Author","values":["Sriram, M."]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2014-12-16T22:23:24Z","10000-01-01","1993"]},{"key":"dc:type","label":"Dc Type","values":["text"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Electrical Engineering"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Dissertation"]},{"key":"thesis:degree_name","label":"Degree Name","values":["Ph.D."]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["University of Illinois at Urbana-Champaign"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Engineering, Electronics and Electrical"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["http://hdl.handle.net/2142/72024","(UMI)AAI9411790"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["This thesis deals with four physical design problems in the multichip module (MCM) environment: interconnect analysis, chip placement, global tree construction, and layer assignment. The emphasis is on maximizing the electrical performance, based on accurate modeling of MCM interconnect behavior. A new approach, called Reciprocal Expansion, is developed for rapidly estimating the time-domain response of lossy coupled MCM interconnect structures, and its accuracy and efficiency are demonstrated experimentally. A second-order RLC delay model is presented, which captures the effects of line resistance and inductance on signal delay. A "resistance-driven" chip placement algorithm is described, which takes interconnect resistance into account to find a placement with minimum net delays. Multilayer MCM routing is decomposed into two stages: two-dimensional global tree construction and layer assignment. An algorithm for global tree construction is presented, which attempts to minimize the number and length of stubs, while simultaneously minimizing the second-order delay. Finally, the layer assignment problem is considered. A model for the multilayer ceramic MCM environment is developed. Theoretical results on the complexity of the layer assignment problem on this model are derived, and an effective heuristic algorithm is presented. A second approach to layer assignment, based on max-cut partitioning of a net interference graph, is also studied. New techniques for constructing the interference graph based on congestion and crosstalk are presented, and algorithms for max-cut partitioning and crosstalk minimization are described.","Made available in DSpace on 2014-12-16T22:23:24Z (GMT). No. of bitstreams: 1 9411790.pdf: 6431270 bytes, checksum: 1f7715cac626a41ffa823b9d13e1fff2 (MD5) Previous issue date: 1993","Embargo set by: Seth Robbins for item 72190 Lift date: Forever Reason: Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs","Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs","U of I Only","172 p.","Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1993."]},{"key":"dc:title","label":"Title","values":["Physical Design for Multichip Modules"]}]}],"canonical_facts":{"dc:contributor":["Kang, S.M."],"dc:creator":["Sriram, M."],"dc:date":["2014-12-16T22:23:24Z","10000-01-01","1993"],"dc:description":["This thesis deals with four physical design problems in the multichip module (MCM) environment: interconnect analysis, chip placement, global tree construction, and layer assignment. The emphasis is on maximizing the electrical performance, based on accurate modeling of MCM interconnect behavior. A new approach, called Reciprocal Expansion, is developed for rapidly estimating the time-domain response of lossy coupled MCM interconnect structures, and its accuracy and efficiency are demonstrated experimentally. A second-order RLC delay model is presented, which captures the effects of line resistance and inductance on signal delay. A "resistance-driven" chip placement algorithm is described, which takes interconnect resistance into account to find a placement with minimum net delays. Multilayer MCM routing is decomposed into two stages: two-dimensional global tree construction and layer assignment. An algorithm for global tree construction is presented, which attempts to minimize the number and length of stubs, while simultaneously minimizing the second-order delay. Finally, the layer assignment problem is considered. A model for the multilayer ceramic MCM environment is developed. Theoretical results on the complexity of the layer assignment problem on this model are derived, and an effective heuristic algorithm is presented. A second approach to layer assignment, based on max-cut partitioning of a net interference graph, is also studied. New techniques for constructing the interference graph based on congestion and crosstalk are presented, and algorithms for max-cut partitioning and crosstalk minimization are described.","Made available in DSpace on 2014-12-16T22:23:24Z (GMT). No. of bitstreams: 1 9411790.pdf: 6431270 bytes, checksum: 1f7715cac626a41ffa823b9d13e1fff2 (MD5) Previous issue date: 1993","Embargo set by: Seth Robbins for item 72190 Lift date: Forever Reason: Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs","Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs","U of I Only","172 p.","Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1993."],"dc:identifier":["http://hdl.handle.net/2142/72024","(UMI)AAI9411790"],"dc:subject":["Engineering, Electronics and Electrical"],"dc:title":["Physical Design for Multichip Modules"],"dc:type":["text"],"thesis:degree_discipline":["Electrical Engineering"],"thesis:degree_level":["Dissertation"],"thesis:degree_name":["Ph.D."],"thesis:institution_name":["University of Illinois at Urbana-Champaign"]},"updated_at":"2026-07-22T22:26:06Z"}