{"id":{"repo_id":"uiuc","oai_identifier":"oai:www.ideals.illinois.edu:2142/69566"},"canonical_url":"https://search.dev.ndltd.org/etd/uiuc/oai:www.ideals.illinois.edu:2142/69566","repository":{"repo_id":"uiuc","name":"University of Illinois - Urbana-Champaign","base_url":"https://www.ideals.illinois.edu/oai-pmh"},"display":{"title":"Fault-Tolerant Multiprocessor Interconnection Networks and Their Fault-Diagnoses","abstract":"Interconnection networks have long been recognized as one of the key issues in designing a multiprocessor. A new scheme to provide multistage interconnection networks with fault-tolerance is introduced. Multiple paths between any input/output pair are created by connecting switching elements in the same stage together. The fault-tolerant interconnection network is investigated in both its reliability and its performance. Because the maximum number of possible alternative paths inherent in a network is exploited, the proposed fault-tolerant network possesses long mean lifetime and demonstrates high bandwidth. This scheme can be applied to notably enhance reliability and performance of any known multistage interconnection networks.","abstract_html":"Interconnection networks have long been recognized as one of the key issues in designing a multiprocessor. A new scheme to provide multistage interconnection networks with fault-tolerance is introduced. Multiple paths between any input/output pair are created by connecting switching elements in the same stage together. The fault-tolerant interconnection network is investigated in both its reliability and its performance. Because the maximum number of possible alternative paths inherent in a network is exploited, the proposed fault-tolerant network possesses long mean lifetime and demonstrates high bandwidth. This scheme can be applied to notably enhance reliability and performance of any known multistage interconnection networks.","abstract_has_math":false,"creators":["Tzeng, Nian-Feng"],"institution":"University of Illinois at Urbana-Champaign","degree_name":"Ph.D.","degree_level":"Dissertation","degree_discipline":"Computer Science","degree_department":null,"school":null,"contributors":[],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2014,"date_issued":"2014-12-15T19:25:50Z","date_published":"2014-12-15T19:25:50Z","updated_at":"2026-07-22T22:26:01Z","subjects":["Computer Science"],"languages":[],"rights":[],"rights_urls":[],"identifier_entries":[{"key":"dc:identifier","label":"Identifier","values":["(UMI)AAI8701640"],"render_values":[{"text":"(UMI)AAI8701640","href":null,"code":true}]}]},"links":{"outbound_url":"http://hdl.handle.net/2142/69566","outbound_label":"Handle","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:creator","label":"Author","values":["Tzeng, Nian-Feng"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2014-12-15T19:25:50Z","10000-01-01","1986"]},{"key":"dc:type","label":"Dc Type","values":["text"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Computer Science"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Dissertation"]},{"key":"thesis:degree_name","label":"Degree Name","values":["Ph.D."]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["University of Illinois at Urbana-Champaign"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Computer Science"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["http://hdl.handle.net/2142/69566","(UMI)AAI8701640"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["Interconnection networks have long been recognized as one of the key issues in designing a multiprocessor. A new scheme to provide multistage interconnection networks with fault-tolerance is introduced. Multiple paths between any input/output pair are created by connecting switching elements in the same stage together. The fault-tolerant interconnection network is investigated in both its reliability and its performance. Because the maximum number of possible alternative paths inherent in a network is exploited, the proposed fault-tolerant network possesses long mean lifetime and demonstrates high bandwidth. This scheme can be applied to notably enhance reliability and performance of any known multistage interconnection networks.","To diagnose a fault in a redundant-path interconnection network is far more involved than in a regular one. Based on a novel fault-model, a diagnostic procedure is developed to effectively detect and locate any single fault existing in the multiple-path network. The fault-model is practical and has potential usefulness as a tool for modeling faulty states of larger switching elements (e.g., n x n switching elements with n > 2). To facilitate this procedure, faults are classified into two groups in each of which the necessary test vectors are provided for correctly setting switching elements in the network under diagnosis when the procedure is conducted.","Made available in DSpace on 2014-12-15T19:25:50Z (GMT). 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Multiple paths between any input/output pair are created by connecting switching elements in the same stage together. The fault-tolerant interconnection network is investigated in both its reliability and its performance. Because the maximum number of possible alternative paths inherent in a network is exploited, the proposed fault-tolerant network possesses long mean lifetime and demonstrates high bandwidth. This scheme can be applied to notably enhance reliability and performance of any known multistage interconnection networks.","To diagnose a fault in a redundant-path interconnection network is far more involved than in a regular one. Based on a novel fault-model, a diagnostic procedure is developed to effectively detect and locate any single fault existing in the multiple-path network. The fault-model is practical and has potential usefulness as a tool for modeling faulty states of larger switching elements (e.g., n x n switching elements with n > 2). To facilitate this procedure, faults are classified into two groups in each of which the necessary test vectors are provided for correctly setting switching elements in the network under diagnosis when the procedure is conducted.","Made available in DSpace on 2014-12-15T19:25:50Z (GMT). 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