{"id":{"repo_id":"uiuc","oai_identifier":"oai:www.ideals.illinois.edu:2142/69556"},"canonical_url":"https://search.dev.ndltd.org/etd/uiuc/oai:www.ideals.illinois.edu:2142/69556","repository":{"repo_id":"uiuc","name":"University of Illinois - Urbana-Champaign","base_url":"https://www.ideals.illinois.edu/oai-pmh"},"display":{"title":"Automatic Random Logic Layout Synthesis - a Module Generator Approach (Vlsi, Silicon Compilation, Design Automation, Cell Synthesis, Grid)","abstract":"A new approach is introduced for solving the automatic random logic layout synthesis problem. The emphasis is on the global optimization which requires that partitioning, placement and synthesis schemes consider the two-dimensional nature of the problem. Divide-and-conquer principle is used for partitioning the logic into small cells. The placement and wire assignment scheme propagates the structural constraints of the module to the lowest level cells. Cells are then custom-synthesized under those structural constraints by the cell synthesizer. The cell synthesizer uses one-dimensional cell structures and new efficient linear-time algorithms based on the interval graph optimization for producing an optimal layout on the virtual grid and experiments layout synthesis on virtual grids under multiple structural constraints.","abstract_html":"A new approach is introduced for solving the automatic random logic layout synthesis problem. The emphasis is on the global optimization which requires that partitioning, placement and synthesis schemes consider the two-dimensional nature of the problem. Divide-and-conquer principle is used for partitioning the logic into small cells. The placement and wire assignment scheme propagates the structural constraints of the module to the lowest level cells. Cells are then custom-synthesized under those structural constraints by the cell synthesizer. The cell synthesizer uses one-dimensional cell structures and new efficient linear-time algorithms based on the interval graph optimization for producing an optimal layout on the virtual grid and experiments layout synthesis on virtual grids under multiple structural constraints.","abstract_has_math":false,"creators":["Yu, Meng-Lin"],"institution":"University of Illinois at Urbana-Champaign","degree_name":"Ph.D.","degree_level":"Dissertation","degree_discipline":"Computer Science","degree_department":null,"school":null,"contributors":[],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2014,"date_issued":"2014-12-15T19:25:45Z","date_published":"2014-12-15T19:25:45Z","updated_at":"2026-07-22T22:26:01Z","subjects":["Computer Science"],"languages":[],"rights":[],"rights_urls":[],"identifier_entries":[{"key":"dc:identifier","label":"Identifier","values":["(UMI)AAI8623445"],"render_values":[{"text":"(UMI)AAI8623445","href":null,"code":true}]}]},"links":{"outbound_url":"http://hdl.handle.net/2142/69556","outbound_label":"Handle","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:creator","label":"Author","values":["Yu, Meng-Lin"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2014-12-15T19:25:45Z","10000-01-01","1986"]},{"key":"dc:type","label":"Dc Type","values":["text"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Computer Science"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Dissertation"]},{"key":"thesis:degree_name","label":"Degree Name","values":["Ph.D."]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["University of Illinois at Urbana-Champaign"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Computer Science"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["http://hdl.handle.net/2142/69556","(UMI)AAI8623445"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["A new approach is introduced for solving the automatic random logic layout synthesis problem. The emphasis is on the global optimization which requires that partitioning, placement and synthesis schemes consider the two-dimensional nature of the problem. Divide-and-conquer principle is used for partitioning the logic into small cells. The placement and wire assignment scheme propagates the structural constraints of the module to the lowest level cells. Cells are then custom-synthesized under those structural constraints by the cell synthesizer. The cell synthesizer uses one-dimensional cell structures and new efficient linear-time algorithms based on the interval graph optimization for producing an optimal layout on the virtual grid and experiments layout synthesis on virtual grids under multiple structural constraints.","The effectiveness of imposing relative I/O ordering constraints is supported by the experimental data. Routing area reduction usually more than compensates for the cell area penalty. Smaller than quadratic area growth rate for cell synthesis has been observed. Experience suggests that this approach is a viable and promising one for VLSI layout synthesis.","Made available in DSpace on 2014-12-15T19:25:45Z (GMT). No. of bitstreams: 1 8623445.pdf: 4467909 bytes, checksum: 94443770b92fae38e0eef9ad4054a425 (MD5) Previous issue date: 1986","Embargo set by: Seth Robbins for item 69722 Lift date: Forever Reason: Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs","Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs","U of I Only","158 p.","Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1986."]},{"key":"dc:title","label":"Title","values":["Automatic Random Logic Layout Synthesis - a Module Generator Approach (Vlsi, Silicon Compilation, Design Automation, Cell Synthesis, Grid)"]}]}],"canonical_facts":{"dc:creator":["Yu, Meng-Lin"],"dc:date":["2014-12-15T19:25:45Z","10000-01-01","1986"],"dc:description":["A new approach is introduced for solving the automatic random logic layout synthesis problem. The emphasis is on the global optimization which requires that partitioning, placement and synthesis schemes consider the two-dimensional nature of the problem. Divide-and-conquer principle is used for partitioning the logic into small cells. The placement and wire assignment scheme propagates the structural constraints of the module to the lowest level cells. Cells are then custom-synthesized under those structural constraints by the cell synthesizer. The cell synthesizer uses one-dimensional cell structures and new efficient linear-time algorithms based on the interval graph optimization for producing an optimal layout on the virtual grid and experiments layout synthesis on virtual grids under multiple structural constraints.","The effectiveness of imposing relative I/O ordering constraints is supported by the experimental data. Routing area reduction usually more than compensates for the cell area penalty. Smaller than quadratic area growth rate for cell synthesis has been observed. Experience suggests that this approach is a viable and promising one for VLSI layout synthesis.","Made available in DSpace on 2014-12-15T19:25:45Z (GMT). No. of bitstreams: 1 8623445.pdf: 4467909 bytes, checksum: 94443770b92fae38e0eef9ad4054a425 (MD5) Previous issue date: 1986","Embargo set by: Seth Robbins for item 69722 Lift date: Forever Reason: Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs","Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs","U of I Only","158 p.","Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1986."],"dc:identifier":["http://hdl.handle.net/2142/69556","(UMI)AAI8623445"],"dc:subject":["Computer Science"],"dc:title":["Automatic Random Logic Layout Synthesis - a Module Generator Approach (Vlsi, Silicon Compilation, Design Automation, Cell Synthesis, Grid)"],"dc:type":["text"],"thesis:degree_discipline":["Computer Science"],"thesis:degree_level":["Dissertation"],"thesis:degree_name":["Ph.D."],"thesis:institution_name":["University of Illinois at Urbana-Champaign"]},"updated_at":"2026-07-22T22:26:01Z"}