Methods for Cell Compilation With Constraints (Vlsi, Pla, Routing, Silicon)
type: CreativeWork
description: One method in solving the VLSI layout problems is a library of standard cells which are used as standard building blocks. Therefore, the design problem is partitioned into two subproblems: (a) decomposition of design into standard cells and (b) placement and routing of standard cells used in the design. The first problem of standard-cell methodology is that library has to be maintained and updated because each cell is usually needed in many different versions. All of them have the same functionality but slightly different in electrical charateristics (time delay, power consumption), geometrical characteristics (height, width) and the position of each input/output. The solution to this problem is a library of parametrized cells.
abstract: One method in solving the VLSI layout problems is a library of standard cells which are used as standard building blocks. Therefore, the design problem is partitioned into two subproblems: (a) decomposition of design into standard cells and (b) placement and routing of standard cells used in the design. The first problem of standard-cell methodology is that library has to be maintained and updated because each cell is usually needed in many different versions. All of them have the same functionality but slightly different in electrical charateristics (time delay, power consumption), geometrical characteristics (height, width) and the position of each input/output. The solution to this problem is a library of parametrized cells.
author: Lursinsap, Chidchanok
keywords: Computer Science
date published: 2014-12-15T19:25:43Z
date modified: 2026-07-22T22:26:01Z
provider: University of Illinois - Urbana-Champaign
publisher: Networked Digital Library of Theses and Dissertations
type: WebPage
source organization: University of Illinois at Urbana-Champaign

PropertyValue
property ID: Handle
value: http://hdl.handle.net/2142/69552