{"id":{"repo_id":"uiuc","oai_identifier":"oai:www.ideals.illinois.edu:2142/69549"},"canonical_url":"https://search.dev.ndltd.org/etd/uiuc/oai:www.ideals.illinois.edu:2142/69549","repository":{"repo_id":"uiuc","name":"University of Illinois - Urbana-Champaign","base_url":"https://www.ideals.illinois.edu/oai-pmh"},"display":{"title":"Routing Problems in the Physical Design of Integrated Circuits (Cad, Simulated Annealing, Channel Routing)","abstract":"In this thesis, we study an approach to the physical design of integrated circuits in which some design flexibilities are incorporated into the routing step via suitable generalizations of the routing model. Better layouts are obtained using this approach since the router can make use of these flexibilities to reduce the wiring area.","abstract_html":"In this thesis, we study an approach to the physical design of integrated circuits in which some design flexibilities are incorporated into the routing step via suitable generalizations of the routing model. Better layouts are obtained using this approach since the router can make use of these flexibilities to reduce the wiring area.","abstract_has_math":false,"creators":["Leong, Hon Wai"],"institution":"University of Illinois at Urbana-Champaign","degree_name":"Ph.D.","degree_level":"Dissertation","degree_discipline":"Computer Science","degree_department":null,"school":null,"contributors":[],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2014,"date_issued":"2014-12-15T19:25:42Z","date_published":"2014-12-15T19:25:42Z","updated_at":"2026-07-22T22:26:01Z","subjects":["Computer Science"],"languages":[],"rights":[],"rights_urls":[],"identifier_entries":[{"key":"dc:identifier","label":"Identifier","values":["(UMI)AAI8610954"],"render_values":[{"text":"(UMI)AAI8610954","href":null,"code":true}]}]},"links":{"outbound_url":"http://hdl.handle.net/2142/69549","outbound_label":"Handle","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:creator","label":"Author","values":["Leong, Hon Wai"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2014-12-15T19:25:42Z","10000-01-01","1986"]},{"key":"dc:type","label":"Dc Type","values":["text"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Computer Science"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Dissertation"]},{"key":"thesis:degree_name","label":"Degree Name","values":["Ph.D."]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["University of Illinois at Urbana-Champaign"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Computer Science"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["http://hdl.handle.net/2142/69549","(UMI)AAI8610954"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["In this thesis, we study an approach to the physical design of integrated circuits in which some design flexibilities are incorporated into the routing step via suitable generalizations of the routing model. Better layouts are obtained using this approach since the router can make use of these flexibilities to reduce the wiring area.","Three different models for channel routing are considered--traditional channel routing, and generalizations to discretionary channel routing where we only require that each net connect some (not all) of its pins, and permutation channel routing where we allow some of the pins to be interchanged. We show that these generalizations can handle design flexibilities such as physically and logically equivalent pins, duplicated pins in macrocells, and input/output in assignments in programmable logic devices.","For the traditional model, we present a new simulated annealing channel routing algorithm whose performance is competitive with other well-known channel routers in the literature. Efficient algorithms for the discretionary and permutation channel routing problems are also presented. These algorithms have been implemented and tested on various data and our results show that they produce near-optimal solutions. More importantly, these results show that substantial savings in the wiring area can be achieved by using the generalized models.","Made available in DSpace on 2014-12-15T19:25:42Z (GMT). No. of bitstreams: 1 8610954.pdf: 5888778 bytes, checksum: dfca6bd78b309cb21c9ba2a7f6b4a4e1 (MD5) Previous issue date: 1986","Embargo set by: Seth Robbins for item 69715 Lift date: Forever Reason: Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs","Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs","U of I Only","177 p.","Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1986."]},{"key":"dc:title","label":"Title","values":["Routing Problems in the Physical Design of Integrated Circuits (Cad, Simulated Annealing, Channel Routing)"]}]}],"canonical_facts":{"dc:creator":["Leong, Hon Wai"],"dc:date":["2014-12-15T19:25:42Z","10000-01-01","1986"],"dc:description":["In this thesis, we study an approach to the physical design of integrated circuits in which some design flexibilities are incorporated into the routing step via suitable generalizations of the routing model. Better layouts are obtained using this approach since the router can make use of these flexibilities to reduce the wiring area.","Three different models for channel routing are considered--traditional channel routing, and generalizations to discretionary channel routing where we only require that each net connect some (not all) of its pins, and permutation channel routing where we allow some of the pins to be interchanged. We show that these generalizations can handle design flexibilities such as physically and logically equivalent pins, duplicated pins in macrocells, and input/output in assignments in programmable logic devices.","For the traditional model, we present a new simulated annealing channel routing algorithm whose performance is competitive with other well-known channel routers in the literature. Efficient algorithms for the discretionary and permutation channel routing problems are also presented. These algorithms have been implemented and tested on various data and our results show that they produce near-optimal solutions. More importantly, these results show that substantial savings in the wiring area can be achieved by using the generalized models.","Made available in DSpace on 2014-12-15T19:25:42Z (GMT). No. of bitstreams: 1 8610954.pdf: 5888778 bytes, checksum: dfca6bd78b309cb21c9ba2a7f6b4a4e1 (MD5) Previous issue date: 1986","Embargo set by: Seth Robbins for item 69715 Lift date: Forever Reason: Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs","Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs","U of I Only","177 p.","Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1986."],"dc:identifier":["http://hdl.handle.net/2142/69549","(UMI)AAI8610954"],"dc:subject":["Computer Science"],"dc:title":["Routing Problems in the Physical Design of Integrated Circuits (Cad, Simulated Annealing, Channel Routing)"],"dc:type":["text"],"thesis:degree_discipline":["Computer Science"],"thesis:degree_level":["Dissertation"],"thesis:degree_name":["Ph.D."],"thesis:institution_name":["University of Illinois at Urbana-Champaign"]},"updated_at":"2026-07-22T22:26:01Z"}