{"id":{"repo_id":"uiuc","oai_identifier":"oai:www.ideals.illinois.edu:2142/69540"},"canonical_url":"https://search.dev.ndltd.org/etd/uiuc/oai:www.ideals.illinois.edu:2142/69540","repository":{"repo_id":"uiuc","name":"University of Illinois - Urbana-Champaign","base_url":"https://www.ideals.illinois.edu/oai-pmh"},"display":{"title":"Algorithms for Logic Design Automation (Rtcad, Synthesis)","abstract":"As the complexity of logic circuits which may be placed on an integrated circuit grows, the complexity and length of the design process increases also. Consequently, there have been increased efforts in recent years directed at developing tools to ease design tasks, mostly the physical tasks such as layout and routing. For low volume applications of integrated circuits, where the design costs may greatly exceed the production costs for the production lifetime of the integrated circuit, and especially if the same basic architecture is needed for several designs, it is economically justifiable to develop design tools which are able to produce semi-automatically an integrated circuit which corresponds to a high level behavioral description of a logic circuit. This thesis describes a collection of algorithms that transform a graph data structure derived from a behavior description into a logic design at the register transfer level.","abstract_html":"As the complexity of logic circuits which may be placed on an integrated circuit grows, the complexity and length of the design process increases also. Consequently, there have been increased efforts in recent years directed at developing tools to ease design tasks, mostly the physical tasks such as layout and routing. For low volume applications of integrated circuits, where the design costs may greatly exceed the production costs for the production lifetime of the integrated circuit, and especially if the same basic architecture is needed for several designs, it is economically justifiable to develop design tools which are able to produce semi-automatically an integrated circuit which corresponds to a high level behavioral description of a logic circuit. This thesis describes a collection of algorithms that transform a graph data structure derived from a behavior description into a logic design at the register transfer level.","abstract_has_math":false,"creators":["Casavant, Albert Ernest"],"institution":"University of Illinois at Urbana-Champaign","degree_name":"Ph.D.","degree_level":"Dissertation","degree_discipline":"Computer Science","degree_department":null,"school":null,"contributors":[],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2014,"date_issued":"2014-12-15T19:25:37Z","date_published":"2014-12-15T19:25:37Z","updated_at":"2026-07-22T22:26:01Z","subjects":["Computer Science"],"languages":[],"rights":[],"rights_urls":[],"identifier_entries":[{"key":"dc:identifier","label":"Identifier","values":["(UMI)AAI8511593"],"render_values":[{"text":"(UMI)AAI8511593","href":null,"code":true}]}]},"links":{"outbound_url":"http://hdl.handle.net/2142/69540","outbound_label":"Handle","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:creator","label":"Author","values":["Casavant, Albert Ernest"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2014-12-15T19:25:37Z","10000-01-01","1985"]},{"key":"dc:type","label":"Dc Type","values":["text"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Computer Science"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Dissertation"]},{"key":"thesis:degree_name","label":"Degree Name","values":["Ph.D."]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["University of Illinois at Urbana-Champaign"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Computer Science"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["http://hdl.handle.net/2142/69540","(UMI)AAI8511593"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["As the complexity of logic circuits which may be placed on an integrated circuit grows, the complexity and length of the design process increases also. Consequently, there have been increased efforts in recent years directed at developing tools to ease design tasks, mostly the physical tasks such as layout and routing. For low volume applications of integrated circuits, where the design costs may greatly exceed the production costs for the production lifetime of the integrated circuit, and especially if the same basic architecture is needed for several designs, it is economically justifiable to develop design tools which are able to produce semi-automatically an integrated circuit which corresponds to a high level behavioral description of a logic circuit. This thesis describes a collection of algorithms that transform a graph data structure derived from a behavior description into a logic design at the register transfer level.","The proposed design system creates register transfer level designs using numbers and types of resources controlled, for the most part, by the user of the system. The overall architecture of the data part (i.e. a multiple functional unit, multiple bus configuration) and the control part (i.e. microprogrammed) are fixed by the system. The user has control over the number and type of functional units, the number of buses, the length of the microword and the number and type of microcode sequencing instructions.","The design process proceeds as follows: functional units are scheduled into microinstructions without violating precedence or resource constraints with the objective of minimizing schedule length i.e. the number of microinstructions required to execute the behavioral description. When scheduling is completed, actual register files are assigned to file uses determined during scheduling in such a way as to avoid file conflicts and minimize the total number of registers used to store intermediate results.","Methods are presented to minimize the number of NOPs generated in microcode and to place those which are needed into low execution frequency locations in microcode. Finally, multiplexing between buses and functional units and at the output of the microword is heuristically minimized.","Made available in DSpace on 2014-12-15T19:25:37Z (GMT). No. of bitstreams: 1 8511593.pdf: 8417839 bytes, checksum: 56556ca1dc4f524f54451d45c40a35da (MD5) Previous issue date: 1985","Embargo set by: Seth Robbins for item 69706 Lift date: Forever Reason: Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs","Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs","U of I Only","315 p.","Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1985."]},{"key":"dc:title","label":"Title","values":["Algorithms for Logic Design Automation (Rtcad, Synthesis)"]}]}],"canonical_facts":{"dc:creator":["Casavant, Albert Ernest"],"dc:date":["2014-12-15T19:25:37Z","10000-01-01","1985"],"dc:description":["As the complexity of logic circuits which may be placed on an integrated circuit grows, the complexity and length of the design process increases also. Consequently, there have been increased efforts in recent years directed at developing tools to ease design tasks, mostly the physical tasks such as layout and routing. For low volume applications of integrated circuits, where the design costs may greatly exceed the production costs for the production lifetime of the integrated circuit, and especially if the same basic architecture is needed for several designs, it is economically justifiable to develop design tools which are able to produce semi-automatically an integrated circuit which corresponds to a high level behavioral description of a logic circuit. This thesis describes a collection of algorithms that transform a graph data structure derived from a behavior description into a logic design at the register transfer level.","The proposed design system creates register transfer level designs using numbers and types of resources controlled, for the most part, by the user of the system. The overall architecture of the data part (i.e. a multiple functional unit, multiple bus configuration) and the control part (i.e. microprogrammed) are fixed by the system. The user has control over the number and type of functional units, the number of buses, the length of the microword and the number and type of microcode sequencing instructions.","The design process proceeds as follows: functional units are scheduled into microinstructions without violating precedence or resource constraints with the objective of minimizing schedule length i.e. the number of microinstructions required to execute the behavioral description. When scheduling is completed, actual register files are assigned to file uses determined during scheduling in such a way as to avoid file conflicts and minimize the total number of registers used to store intermediate results.","Methods are presented to minimize the number of NOPs generated in microcode and to place those which are needed into low execution frequency locations in microcode. Finally, multiplexing between buses and functional units and at the output of the microword is heuristically minimized.","Made available in DSpace on 2014-12-15T19:25:37Z (GMT). No. of bitstreams: 1 8511593.pdf: 8417839 bytes, checksum: 56556ca1dc4f524f54451d45c40a35da (MD5) Previous issue date: 1985","Embargo set by: Seth Robbins for item 69706 Lift date: Forever Reason: Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs","Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs","U of I Only","315 p.","Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1985."],"dc:identifier":["http://hdl.handle.net/2142/69540","(UMI)AAI8511593"],"dc:subject":["Computer Science"],"dc:title":["Algorithms for Logic Design Automation (Rtcad, Synthesis)"],"dc:type":["text"],"thesis:degree_discipline":["Computer Science"],"thesis:degree_level":["Dissertation"],"thesis:degree_name":["Ph.D."],"thesis:institution_name":["University of Illinois at Urbana-Champaign"]},"updated_at":"2026-07-22T22:26:01Z"}