{"id":{"repo_id":"uiuc","oai_identifier":"oai:www.ideals.illinois.edu:2142/69385"},"canonical_url":"https://search.dev.ndltd.org/etd/uiuc/oai:www.ideals.illinois.edu:2142/69385","repository":{"repo_id":"uiuc","name":"University of Illinois - Urbana-Champaign","base_url":"https://www.ideals.illinois.edu/oai-pmh"},"display":{"title":"Accurate Low-Cost Methods for Performance Evaluation of Cache Memory Systems","abstract":"Trace-driven simulation is a simple way of evaluating cache memory systems with varying hardware parameters. But to evaluate realistic workloads, simulating even a few million addresses is not adequate and such large scale simulation is impractical from the consideration of space and time requirements. In this work, new methods of simulation based on statistical techniques are proposed for decreasing the need for large trace measurements and for predicting true program behavior. In our method, sampling techniques are applied while collecting the address trace from a workload. This drastically reduces the space and time needed to collect the trace. New simulation techniques are developed to use the sampled data not only to predict the mean miss rate of the cache, but also to provide an empirical estimate of its actual distribution. A model is proposed to statistically project the results to different context-switch intervals from only one simulation of a small number of samples of a fixed size. A new concept of primed cache is introduced to simulate large caches by the sampling-based method. Finally, a cache model is developed to study the performance of different split caches.","abstract_html":"Trace-driven simulation is a simple way of evaluating cache memory systems with varying hardware parameters. But to evaluate realistic workloads, simulating even a few million addresses is not adequate and such large scale simulation is impractical from the consideration of space and time requirements. In this work, new methods of simulation based on statistical techniques are proposed for decreasing the need for large trace measurements and for predicting true program behavior. In our method, sampling techniques are applied while collecting the address trace from a workload. This drastically reduces the space and time needed to collect the trace. New simulation techniques are developed to use the sampled data not only to predict the mean miss rate of the cache, but also to provide an empirical estimate of its actual distribution. A model is proposed to statistically project the results to different context-switch intervals from only one simulation of a small number of samples of a fixed size. A new concept of primed cache is introduced to simulate large caches by the sampling-based method. Finally, a cache model is developed to study the performance of different split caches.","abstract_has_math":false,"creators":["Laha, Subhasis"],"institution":"University of Illinois at Urbana-Champaign","degree_name":"Ph.D.","degree_level":"Dissertation","degree_discipline":"Electrical Engineering","degree_department":null,"school":null,"contributors":[],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2014,"date_issued":"2014-12-15T19:05:29Z","date_published":"2014-12-15T19:05:29Z","updated_at":"2026-07-22T22:26:00Z","subjects":["Engineering, Electronics and Electrical","Computer Science"],"languages":[],"rights":[],"rights_urls":[],"identifier_entries":[{"key":"dc:identifier","label":"Identifier","values":["(UMI)AAI8815375"],"render_values":[{"text":"(UMI)AAI8815375","href":null,"code":true}]}]},"links":{"outbound_url":"http://hdl.handle.net/2142/69385","outbound_label":"Handle","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:creator","label":"Author","values":["Laha, Subhasis"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2014-12-15T19:05:29Z","10000-01-01","1988"]},{"key":"dc:type","label":"Dc Type","values":["text"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Electrical Engineering"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Dissertation"]},{"key":"thesis:degree_name","label":"Degree Name","values":["Ph.D."]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["University of Illinois at Urbana-Champaign"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Engineering, Electronics and Electrical","Computer Science"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["http://hdl.handle.net/2142/69385","(UMI)AAI8815375"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["Trace-driven simulation is a simple way of evaluating cache memory systems with varying hardware parameters. But to evaluate realistic workloads, simulating even a few million addresses is not adequate and such large scale simulation is impractical from the consideration of space and time requirements. In this work, new methods of simulation based on statistical techniques are proposed for decreasing the need for large trace measurements and for predicting true program behavior. In our method, sampling techniques are applied while collecting the address trace from a workload. This drastically reduces the space and time needed to collect the trace. New simulation techniques are developed to use the sampled data not only to predict the mean miss rate of the cache, but also to provide an empirical estimate of its actual distribution. A model is proposed to statistically project the results to different context-switch intervals from only one simulation of a small number of samples of a fixed size. A new concept of primed cache is introduced to simulate large caches by the sampling-based method. Finally, a cache model is developed to study the performance of different split caches.","Made available in DSpace on 2014-12-15T19:05:29Z (GMT). No. of bitstreams: 1 8815375.pdf: 2716875 bytes, checksum: 1b5b1fac81f510f226f85879043f08e1 (MD5) Previous issue date: 1988","Embargo set by: Seth Robbins for item 69551 Lift date: Forever Reason: Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs","Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs","U of I Only","86 p.","Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1988."]},{"key":"dc:title","label":"Title","values":["Accurate Low-Cost Methods for Performance Evaluation of Cache Memory Systems"]}]}],"canonical_facts":{"dc:creator":["Laha, Subhasis"],"dc:date":["2014-12-15T19:05:29Z","10000-01-01","1988"],"dc:description":["Trace-driven simulation is a simple way of evaluating cache memory systems with varying hardware parameters. But to evaluate realistic workloads, simulating even a few million addresses is not adequate and such large scale simulation is impractical from the consideration of space and time requirements. In this work, new methods of simulation based on statistical techniques are proposed for decreasing the need for large trace measurements and for predicting true program behavior. In our method, sampling techniques are applied while collecting the address trace from a workload. This drastically reduces the space and time needed to collect the trace. New simulation techniques are developed to use the sampled data not only to predict the mean miss rate of the cache, but also to provide an empirical estimate of its actual distribution. A model is proposed to statistically project the results to different context-switch intervals from only one simulation of a small number of samples of a fixed size. A new concept of primed cache is introduced to simulate large caches by the sampling-based method. Finally, a cache model is developed to study the performance of different split caches.","Made available in DSpace on 2014-12-15T19:05:29Z (GMT). No. of bitstreams: 1 8815375.pdf: 2716875 bytes, checksum: 1b5b1fac81f510f226f85879043f08e1 (MD5) Previous issue date: 1988","Embargo set by: Seth Robbins for item 69551 Lift date: Forever Reason: Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs","Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs","U of I Only","86 p.","Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1988."],"dc:identifier":["http://hdl.handle.net/2142/69385","(UMI)AAI8815375"],"dc:subject":["Engineering, Electronics and Electrical","Computer Science"],"dc:title":["Accurate Low-Cost Methods for Performance Evaluation of Cache Memory Systems"],"dc:type":["text"],"thesis:degree_discipline":["Electrical Engineering"],"thesis:degree_level":["Dissertation"],"thesis:degree_name":["Ph.D."],"thesis:institution_name":["University of Illinois at Urbana-Champaign"]},"updated_at":"2026-07-22T22:26:00Z"}