{"id":{"repo_id":"uiuc","oai_identifier":"oai:www.ideals.illinois.edu:2142/69372"},"canonical_url":"https://search.dev.ndltd.org/etd/uiuc/oai:www.ideals.illinois.edu:2142/69372","repository":{"repo_id":"uiuc","name":"University of Illinois - Urbana-Champaign","base_url":"https://www.ideals.illinois.edu/oai-pmh"},"display":{"title":"Issues in Design for Testability and Self-Test","abstract":"This thesis presents new approaches that enhance testability at the circuit and system level, and a fault-model based aliasing analysis of signature analyzers in random testing.","abstract_html":"This thesis presents new approaches that enhance testability at the circuit and system level, and a fault-model based aliasing analysis of signature analyzers in random testing.","abstract_has_math":false,"creators":["Fujii, Robert"],"institution":"University of Illinois at Urbana-Champaign","degree_name":"Ph.D.","degree_level":"Dissertation","degree_discipline":"Electrical Engineering","degree_department":null,"school":null,"contributors":["Abraham, Jacob A."],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2014,"date_issued":"2014-12-15T19:05:25Z","date_published":"2014-12-15T19:05:25Z","updated_at":"2026-07-22T22:26:00Z","subjects":["Engineering, Electronics and Electrical"],"languages":[],"rights":[],"rights_urls":[],"identifier_entries":[{"key":"dc:identifier","label":"Identifier","values":["(UMI)AAI8803045"],"render_values":[{"text":"(UMI)AAI8803045","href":null,"code":true}]}]},"links":{"outbound_url":"http://hdl.handle.net/2142/69372","outbound_label":"Handle","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Abraham, Jacob A."]},{"key":"dc:creator","label":"Author","values":["Fujii, Robert"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2014-12-15T19:05:25Z","10000-01-01","1987"]},{"key":"dc:type","label":"Dc Type","values":["text"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Electrical Engineering"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Dissertation"]},{"key":"thesis:degree_name","label":"Degree Name","values":["Ph.D."]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["University of Illinois at Urbana-Champaign"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Engineering, Electronics and Electrical"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["http://hdl.handle.net/2142/69372","(UMI)AAI8803045"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["This thesis presents new approaches that enhance testability at the circuit and system level, and a fault-model based aliasing analysis of signature analyzers in random testing.","Past work in circuit and system level testability approaches is extended by (a) Proposing new design for testability approaches for some problems related to logic races, open faults in feedback connections, the long test time required to test counters, and nonadjacent line shorts in the OR array of a programmable logic array (PLA). The proposed redesigns aim to make testing efficient by either avoiding potential test problems or adding some test logic to the circuit in order to shorten test time. (b) Proposing a novel software technique that utilizes microprocessor instructions and data registers to implement signature analyzers and pattern generators. The software implemented test modules can be used to test the sequential behavior of a peripheral control module and to reduce test program size. (c) Proposing a generalized functional fault model for peripheral control modules. Using the functional fault model, test sequences can be derived to detect faults in a peripheral control module when its internal circuit description is unavailable.","An analytical model that relates fault models to the aliasing probability of signature analyzers in the context of random testing is proposed. Multiple error vectors and parallel signature analyzers are modeled. The optimal number of random test patterns needed for fault detection and minimal aliasing is determined. This fault model based analytical approach can be applied to both primitive and nonprimitive polynomial based signature analyzers.","Made available in DSpace on 2014-12-15T19:05:25Z (GMT). No. of bitstreams: 1 8803045.pdf: 3676574 bytes, checksum: 40e90008b949a932dcd7404b9bec3db4 (MD5) Previous issue date: 1987","Embargo set by: Seth Robbins for item 69538 Lift date: Forever Reason: Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs","Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs","U of I Only","121 p.","Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1987."]},{"key":"dc:title","label":"Title","values":["Issues in Design for Testability and Self-Test"]}]}],"canonical_facts":{"dc:contributor":["Abraham, Jacob A."],"dc:creator":["Fujii, Robert"],"dc:date":["2014-12-15T19:05:25Z","10000-01-01","1987"],"dc:description":["This thesis presents new approaches that enhance testability at the circuit and system level, and a fault-model based aliasing analysis of signature analyzers in random testing.","Past work in circuit and system level testability approaches is extended by (a) Proposing new design for testability approaches for some problems related to logic races, open faults in feedback connections, the long test time required to test counters, and nonadjacent line shorts in the OR array of a programmable logic array (PLA). The proposed redesigns aim to make testing efficient by either avoiding potential test problems or adding some test logic to the circuit in order to shorten test time. (b) Proposing a novel software technique that utilizes microprocessor instructions and data registers to implement signature analyzers and pattern generators. The software implemented test modules can be used to test the sequential behavior of a peripheral control module and to reduce test program size. (c) Proposing a generalized functional fault model for peripheral control modules. Using the functional fault model, test sequences can be derived to detect faults in a peripheral control module when its internal circuit description is unavailable.","An analytical model that relates fault models to the aliasing probability of signature analyzers in the context of random testing is proposed. Multiple error vectors and parallel signature analyzers are modeled. The optimal number of random test patterns needed for fault detection and minimal aliasing is determined. This fault model based analytical approach can be applied to both primitive and nonprimitive polynomial based signature analyzers.","Made available in DSpace on 2014-12-15T19:05:25Z (GMT). No. of bitstreams: 1 8803045.pdf: 3676574 bytes, checksum: 40e90008b949a932dcd7404b9bec3db4 (MD5) Previous issue date: 1987","Embargo set by: Seth Robbins for item 69538 Lift date: Forever Reason: Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs","Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs","U of I Only","121 p.","Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1987."],"dc:identifier":["http://hdl.handle.net/2142/69372","(UMI)AAI8803045"],"dc:subject":["Engineering, Electronics and Electrical"],"dc:title":["Issues in Design for Testability and Self-Test"],"dc:type":["text"],"thesis:degree_discipline":["Electrical Engineering"],"thesis:degree_level":["Dissertation"],"thesis:degree_name":["Ph.D."],"thesis:institution_name":["University of Illinois at Urbana-Champaign"]},"updated_at":"2026-07-22T22:26:00Z"}