{"id":{"repo_id":"uiuc","oai_identifier":"oai:www.ideals.illinois.edu:2142/69287"},"canonical_url":"https://search.dev.ndltd.org/etd/uiuc/oai:www.ideals.illinois.edu:2142/69287","repository":{"repo_id":"uiuc","name":"University of Illinois - Urbana-Champaign","base_url":"https://www.ideals.illinois.edu/oai-pmh"},"display":{"title":"A Study of Relaxation Techniques for the Transient Analysis of Digital Circuits","abstract":"In the VLSI microelectronics era, the cost of the immense CPU time and memory storage for a "standard" circuit simulator has become prohibitive. In order to achieve dramatic improvement in the performance of the circuit simulator, there are two principal points of departure from the "standard" simulation approach, namely, "tearing" decomposition and "relaxation" decomposition.('1)","abstract_html":"In the VLSI microelectronics era, the cost of the immense CPU time and memory storage for a "standard" circuit simulator has become prohibitive. In order to achieve dramatic improvement in the performance of the circuit simulator, there are two principal points of departure from the "standard" simulation approach, namely, "tearing" decomposition and "relaxation" decomposition.('1)","abstract_has_math":false,"creators":["Chia, Wei-Kong"],"institution":"University of Illinois at Urbana-Champaign","degree_name":"Ph.D.","degree_level":"Dissertation","degree_discipline":"Electrical Engineering","degree_department":null,"school":null,"contributors":[],"advisors":[],"committee_chairs":[],"committee_members":[],"year":null,"date_issued":"10000-01-01","date_published":"10000-01-01","updated_at":"2026-07-22T22:26:00Z","subjects":["Engineering, Electronics and Electrical"],"languages":[],"rights":[],"rights_urls":[],"identifier_entries":[{"key":"dc:identifier","label":"Identifier","values":["(UMI)AAI8502104"],"render_values":[{"text":"(UMI)AAI8502104","href":null,"code":true}]}]},"links":{"outbound_url":"http://hdl.handle.net/2142/69287","outbound_label":"Handle","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:creator","label":"Author","values":["Chia, Wei-Kong"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["10000-01-01","1984","2014-12-15T19:04:47Z"]},{"key":"dc:type","label":"Dc Type","values":["text"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Electrical Engineering"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Dissertation"]},{"key":"thesis:degree_name","label":"Degree Name","values":["Ph.D."]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["University of Illinois at Urbana-Champaign"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Engineering, Electronics and Electrical"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["http://hdl.handle.net/2142/69287","(UMI)AAI8502104"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["In the VLSI microelectronics era, the cost of the immense CPU time and memory storage for a "standard" circuit simulator has become prohibitive. In order to achieve dramatic improvement in the performance of the circuit simulator, there are two principal points of departure from the "standard" simulation approach, namely, "tearing" decomposition and "relaxation" decomposition.('1)","This research is to study the numerical convergence and stability properties of several of the relaxation algorithms that have been proposed for the simulation of VLSI circuits. The time-point Gauss-Seidel method with prediction, the exploitation of latency and event scheduling algorithms are implemented into a general purpose circuit simulator SLATE-R (a Simulator with Latency and Tearing--Relaxed","version). The performance of the SLATE-R program in the analysis of various types of integrated circuit technologies is studied.","('1)Compared with the conventional techniques, the tearing decomposition is just some special reordering strategy, therefore, it shares the same numerical properties with the conventional techniques. However, the relaxation decomposition processes one subcircuit at a time and relaxes all other subcircuits, therefore, it is characterized by completely different numerical properties.","Made available in DSpace on 2014-12-15T19:04:47Z (GMT). No. of bitstreams: 1 8502104.pdf: 3172832 bytes, checksum: 3e60599be3b193b2ba85364c4696d919 (MD5) Previous issue date: 1984","Embargo set by: Seth Robbins for item 69453 Lift date: Forever Reason: Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs","Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs","U of I Only","154 p.","Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1984."]},{"key":"dc:title","label":"Title","values":["A Study of Relaxation Techniques for the Transient Analysis of Digital Circuits"]}]}],"canonical_facts":{"dc:creator":["Chia, Wei-Kong"],"dc:date":["10000-01-01","1984","2014-12-15T19:04:47Z"],"dc:description":["In the VLSI microelectronics era, the cost of the immense CPU time and memory storage for a "standard" circuit simulator has become prohibitive. In order to achieve dramatic improvement in the performance of the circuit simulator, there are two principal points of departure from the "standard" simulation approach, namely, "tearing" decomposition and "relaxation" decomposition.('1)","This research is to study the numerical convergence and stability properties of several of the relaxation algorithms that have been proposed for the simulation of VLSI circuits. The time-point Gauss-Seidel method with prediction, the exploitation of latency and event scheduling algorithms are implemented into a general purpose circuit simulator SLATE-R (a Simulator with Latency and Tearing--Relaxed","version). The performance of the SLATE-R program in the analysis of various types of integrated circuit technologies is studied.","('1)Compared with the conventional techniques, the tearing decomposition is just some special reordering strategy, therefore, it shares the same numerical properties with the conventional techniques. However, the relaxation decomposition processes one subcircuit at a time and relaxes all other subcircuits, therefore, it is characterized by completely different numerical properties.","Made available in DSpace on 2014-12-15T19:04:47Z (GMT). No. of bitstreams: 1 8502104.pdf: 3172832 bytes, checksum: 3e60599be3b193b2ba85364c4696d919 (MD5) Previous issue date: 1984","Embargo set by: Seth Robbins for item 69453 Lift date: Forever Reason: Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs","Restricted to the U of I community idenfinitely during batch ingest of legacy ETDs","U of I Only","154 p.","Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1984."],"dc:identifier":["http://hdl.handle.net/2142/69287","(UMI)AAI8502104"],"dc:subject":["Engineering, Electronics and Electrical"],"dc:title":["A Study of Relaxation Techniques for the Transient Analysis of Digital Circuits"],"dc:type":["text"],"thesis:degree_discipline":["Electrical Engineering"],"thesis:degree_level":["Dissertation"],"thesis:degree_name":["Ph.D."],"thesis:institution_name":["University of Illinois at Urbana-Champaign"]},"updated_at":"2026-07-22T22:26:00Z"}