{"id":{"repo_id":"uiuc","oai_identifier":"oai:www.ideals.illinois.edu:2142/49852"},"canonical_url":"https://search.dev.ndltd.org/etd/uiuc/oai:www.ideals.illinois.edu:2142/49852","repository":{"repo_id":"uiuc","name":"University of Illinois - Urbana-Champaign","base_url":"https://www.ideals.illinois.edu/oai-pmh"},"display":{"title":"Array-based planar nanowire high electron mobility transistor","abstract":"III-V semiconductor nanowire (NW) field-effect transistors (FETs) are strong candidates for future low-power digital/RF IC. Bottom-up grown NWs via the vapor-liquid-solid (VLS) mechanism are of particular interest for NW-FET application because the as-grown 3D NW structures require no lithography or chemical etching to define. However, fabricating bottom-up NW-FETs and circuits in wafer-scale is still in question. The main challenges include: controllability of NW position, uniformity of NW electrical property, and compatibility with planar processing. In this thesis research, a bottom-up planar-NW high electron mobility transistor (HEMT) technology was developed to overcome the above challenges. Uniform and scalable electrical properties were demonstrated by prototype planar NW HEMTs with multiple 250 nm diameter planar NWs in the channels. Through growth optimization and using a two-temperature-step growth method, defect-free planar GaAs NWs with width as small as 35 nm and tapering factor of better than 1:1000 were achieved. With the down-scaled planar GaAs NWs serving as the channel, a monolithic grown barrier-all-around planar NW HEMT was made with peak G_(m-ext)= 550 µS/µm and I_(d-max)= 435 µA/µm, surpassing its thin-film counterparts. Growth effort with top-down patterned metal catalysts enabled the realization of precisely positioned planar NW arrays in wafer-scale. Having the NW arrays as the channels, planar NW array-based HEMTs were for the first time demonstrated with excellent DC/RF performances: I_on/I_off ~104, SS ~102 mV/dec, DIBL ~151 mV/V and f_T/f_max ~33/75 GHz. To our knowledge, the DC/RF performances achieved here are the best among the nanoscale devices with VLS NWs, carbon nanotubes, or 2D sheets aligned in-plane with the substrate.","abstract_html":"III-V semiconductor nanowire (NW) field-effect transistors (FETs) are strong candidates for future low-power digital/RF IC. Bottom-up grown NWs via the vapor-liquid-solid (VLS) mechanism are of particular interest for NW-FET application because the as-grown 3D NW structures require no lithography or chemical etching to define. However, fabricating bottom-up NW-FETs and circuits in wafer-scale is still in question. The main challenges include: controllability of NW position, uniformity of NW electrical property, and compatibility with planar processing. In this thesis research, a bottom-up planar-NW high electron mobility transistor (HEMT) technology was developed to overcome the above challenges. Uniform and scalable electrical properties were demonstrated by prototype planar NW HEMTs with multiple 250 nm diameter planar NWs in the channels. Through growth optimization and using a two-temperature-step growth method, defect-free planar GaAs NWs with width as small as 35 nm and tapering factor of better than 1:1000 were achieved. With the down-scaled planar GaAs NWs serving as the channel, a monolithic grown barrier-all-around planar NW HEMT was made with peak G_(m-ext)= 550 µS/µm and I_(d-max)= 435 µA/µm, surpassing its thin-film counterparts. Growth effort with top-down patterned metal catalysts enabled the realization of precisely positioned planar NW arrays in wafer-scale. Having the NW arrays as the channels, planar NW array-based HEMTs were for the first time demonstrated with excellent DC/RF performances: I_on/I_off ~104, SS ~102 mV/dec, DIBL ~151 mV/V and f_T/f_max ~33/75 GHz. To our knowledge, the DC/RF performances achieved here are the best among the nanoscale devices with VLS NWs, carbon nanotubes, or 2D sheets aligned in-plane with the substrate.","abstract_has_math":false,"creators":["Miao, Xin"],"institution":"University of Illinois at Urbana-Champaign","degree_name":"Ph.D.","degree_level":"Dissertation","degree_discipline":"Electrical & Computer Engr","degree_department":null,"school":null,"contributors":["Li, Xiuling","Lyding, Joseph W.","Rogers, John A.","Shanbhag, Naresh R."],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2014,"date_issued":"2014-05-30T17:21:04Z","date_published":"2014-05-30T17:21:04Z","updated_at":"2026-07-22T22:25:40Z","subjects":["planar nanowire","III-V","Gallium Arsenide (GaAs)","high-electron-mobility transistor","Radio frequency (RF)","Vapor-liquid-solid (VLSI)"],"languages":["en"],"rights":["Copyright 2014 Xin Miao"],"rights_urls":[],"identifier_entries":[]},"links":{"outbound_url":"http://hdl.handle.net/2142/49852","outbound_label":"Handle","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Li, Xiuling","Lyding, Joseph W.","Rogers, John A.","Shanbhag, Naresh R."]},{"key":"dc:creator","label":"Author","values":["Miao, Xin"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2014-05-30T17:21:04Z","2016-09-22T20:59:25Z","2014-05"]},{"key":"dc:type","label":"Dc Type","values":["text"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Electrical & Computer Engr"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Dissertation"]},{"key":"thesis:degree_name","label":"Degree Name","values":["Ph.D."]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["University of Illinois at Urbana-Champaign"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["planar nanowire","III-V","Gallium Arsenide (GaAs)","high-electron-mobility transistor","Radio frequency (RF)","Vapor-liquid-solid (VLSI)"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language","label":"Dc Language","values":["en"]},{"key":"dc:rights","label":"Dc Rights","values":["Copyright 2014 Xin Miao"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["http://hdl.handle.net/2142/49852"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["III-V semiconductor nanowire (NW) field-effect transistors (FETs) are strong candidates for future low-power digital/RF IC. Bottom-up grown NWs via the vapor-liquid-solid (VLS) mechanism are of particular interest for NW-FET application because the as-grown 3D NW structures require no lithography or chemical etching to define. However, fabricating bottom-up NW-FETs and circuits in wafer-scale is still in question. The main challenges include: controllability of NW position, uniformity of NW electrical property, and compatibility with planar processing. In this thesis research, a bottom-up planar-NW high electron mobility transistor (HEMT) technology was developed to overcome the above challenges. Uniform and scalable electrical properties were demonstrated by prototype planar NW HEMTs with multiple 250 nm diameter planar NWs in the channels. Through growth optimization and using a two-temperature-step growth method, defect-free planar GaAs NWs with width as small as 35 nm and tapering factor of better than 1:1000 were achieved. With the down-scaled planar GaAs NWs serving as the channel, a monolithic grown barrier-all-around planar NW HEMT was made with peak G_(m-ext)= 550 µS/µm and I_(d-max)= 435 µA/µm, surpassing its thin-film counterparts. Growth effort with top-down patterned metal catalysts enabled the realization of precisely positioned planar NW arrays in wafer-scale. Having the NW arrays as the channels, planar NW array-based HEMTs were for the first time demonstrated with excellent DC/RF performances: I_on/I_off ~104, SS ~102 mV/dec, DIBL ~151 mV/V and f_T/f_max ~33/75 GHz. To our knowledge, the DC/RF performances achieved here are the best among the nanoscale devices with VLS NWs, carbon nanotubes, or 2D sheets aligned in-plane with the substrate.","Item withdrawn by Mark Zulauf (zulauf@illinois.edu) on 2014-04-24T17:50:15Z Item was in collections: University of Illinois Theses & Dissertations (ID: 1) No. of bitstreams: 3 Miao_Xin.docx: 22687337 bytes, checksum: b2edf55a144680934d16efcf579878ac (MD5) Miao_Xin.pdf.pdf: 3336509 bytes, checksum: 24daec79aae1d5a16a8c60ac2f0d294d (MD5) Miao_Xin.pdf: 3336509 bytes, checksum: 24daec79aae1d5a16a8c60ac2f0d294d (MD5)","Made available in DSpace on 2014-05-30T17:21:04Z (GMT). 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Bottom-up grown NWs via the vapor-liquid-solid (VLS) mechanism are of particular interest for NW-FET application because the as-grown 3D NW structures require no lithography or chemical etching to define. However, fabricating bottom-up NW-FETs and circuits in wafer-scale is still in question. The main challenges include: controllability of NW position, uniformity of NW electrical property, and compatibility with planar processing. In this thesis research, a bottom-up planar-NW high electron mobility transistor (HEMT) technology was developed to overcome the above challenges. Uniform and scalable electrical properties were demonstrated by prototype planar NW HEMTs with multiple 250 nm diameter planar NWs in the channels. Through growth optimization and using a two-temperature-step growth method, defect-free planar GaAs NWs with width as small as 35 nm and tapering factor of better than 1:1000 were achieved. With the down-scaled planar GaAs NWs serving as the channel, a monolithic grown barrier-all-around planar NW HEMT was made with peak G_(m-ext)= 550 µS/µm and I_(d-max)= 435 µA/µm, surpassing its thin-film counterparts. Growth effort with top-down patterned metal catalysts enabled the realization of precisely positioned planar NW arrays in wafer-scale. Having the NW arrays as the channels, planar NW array-based HEMTs were for the first time demonstrated with excellent DC/RF performances: I_on/I_off ~104, SS ~102 mV/dec, DIBL ~151 mV/V and f_T/f_max ~33/75 GHz. To our knowledge, the DC/RF performances achieved here are the best among the nanoscale devices with VLS NWs, carbon nanotubes, or 2D sheets aligned in-plane with the substrate.","Item withdrawn by Mark Zulauf (zulauf@illinois.edu) on 2014-04-24T17:50:15Z Item was in collections: University of Illinois Theses & Dissertations (ID: 1) No. of bitstreams: 3 Miao_Xin.docx: 22687337 bytes, checksum: b2edf55a144680934d16efcf579878ac (MD5) Miao_Xin.pdf.pdf: 3336509 bytes, checksum: 24daec79aae1d5a16a8c60ac2f0d294d (MD5) Miao_Xin.pdf: 3336509 bytes, checksum: 24daec79aae1d5a16a8c60ac2f0d294d (MD5)","Made available in DSpace on 2014-05-30T17:21:04Z (GMT). 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