{"id":{"repo_id":"uiuc","oai_identifier":"oai:www.ideals.illinois.edu:2142/45391"},"canonical_url":"https://search.dev.ndltd.org/etd/uiuc/oai:www.ideals.illinois.edu:2142/45391","repository":{"repo_id":"uiuc","name":"University of Illinois - Urbana-Champaign","base_url":"https://www.ideals.illinois.edu/oai-pmh"},"display":{"title":"Planar nanowire high electron mobility transistor and down-scaling of planar nanowire","abstract":"Monolithically grown planar nanowire (NW) high electron mobility transistors (NW-HEMTs) have been demonstrated with self-aligned <110> planar GaAs NW channels capped by a thin film AlGaAs barrier. The planar NW-HEMTs exhibit uniform and scalable DC characteristics; and resolve the electrical non-uniformity issues in VLS grown NW-FETs with doped NW channels. Growth optimization through mapping the parameters of group III flow, V/III ratio and temperature has also been successfully done for the realization of high-quality down-scaled planar GaAs NWs with widths as small as 35 nm. With further development of our planar NW technology, wafer-scale low-power and high-speed VLSI circuits involving 3D planar NW channel from the bottom-up is promising.","abstract_html":"Monolithically grown planar nanowire (NW) high electron mobility transistors (NW-HEMTs) have been demonstrated with self-aligned &lt;110&gt; planar GaAs NW channels capped by a thin film AlGaAs barrier. The planar NW-HEMTs exhibit uniform and scalable DC characteristics; and resolve the electrical non-uniformity issues in VLS grown NW-FETs with doped NW channels. Growth optimization through mapping the parameters of group III flow, V/III ratio and temperature has also been successfully done for the realization of high-quality down-scaled planar GaAs NWs with widths as small as 35 nm. With further development of our planar NW technology, wafer-scale low-power and high-speed VLSI circuits involving 3D planar NW channel from the bottom-up is promising.","abstract_has_math":false,"creators":["Miao, Xin"],"institution":"University of Illinois at Urbana-Champaign","degree_name":"M.S.","degree_level":"Thesis","degree_discipline":"Electrical & Computer Engr","degree_department":null,"school":null,"contributors":["Li, Xiuling"],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2013,"date_issued":"2013-08-22T16:38:48Z","date_published":"2013-08-22T16:38:48Z","updated_at":"2026-07-22T22:25:34Z","subjects":["Gallium Arsenide (GaAs)","planar nanowire","High Electron Mobility Transistor (HEMT)","III-V","Very-large-scale integration (VLSI)","micro-tube","resonator"],"languages":["en"],"rights":["Copyright 2013 Xin Miao"],"rights_urls":[],"identifier_entries":[]},"links":{"outbound_url":"http://hdl.handle.net/2142/45391","outbound_label":"Handle","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Li, Xiuling"]},{"key":"dc:creator","label":"Author","values":["Miao, Xin"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2013-08-22T16:38:48Z","2013-08"]},{"key":"dc:type","label":"Dc Type","values":["text"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Electrical & Computer Engr"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Thesis"]},{"key":"thesis:degree_name","label":"Degree Name","values":["M.S."]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["University of Illinois at Urbana-Champaign"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Gallium Arsenide (GaAs)","planar nanowire","High Electron Mobility Transistor (HEMT)","III-V","Very-large-scale integration (VLSI)","micro-tube","resonator"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language","label":"Dc Language","values":["en"]},{"key":"dc:rights","label":"Dc Rights","values":["Copyright 2013 Xin Miao"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["http://hdl.handle.net/2142/45391"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["Monolithically grown planar nanowire (NW) high electron mobility transistors (NW-HEMTs) have been demonstrated with self-aligned <110> planar GaAs NW channels capped by a thin film AlGaAs barrier. The planar NW-HEMTs exhibit uniform and scalable DC characteristics; and resolve the electrical non-uniformity issues in VLS grown NW-FETs with doped NW channels. Growth optimization through mapping the parameters of group III flow, V/III ratio and temperature has also been successfully done for the realization of high-quality down-scaled planar GaAs NWs with widths as small as 35 nm. With further development of our planar NW technology, wafer-scale low-power and high-speed VLSI circuits involving 3D planar NW channel from the bottom-up is promising.","Item withdrawn by Mark Zulauf (zulauf@illinois.edu) on 2013-07-19T18:59:22Z Item was in collections: University of Illinois Theses & Dissertations (ID: 1) No. of bitstreams: 1 Miao_Xin.pdf: 2247519 bytes, checksum: 1d94454975d3f21cfc26dc21419fbe9d (MD5)","Made available in DSpace on 2013-08-22T16:38:48Z (GMT). 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Growth optimization through mapping the parameters of group III flow, V/III ratio and temperature has also been successfully done for the realization of high-quality down-scaled planar GaAs NWs with widths as small as 35 nm. With further development of our planar NW technology, wafer-scale low-power and high-speed VLSI circuits involving 3D planar NW channel from the bottom-up is promising.","Item withdrawn by Mark Zulauf (zulauf@illinois.edu) on 2013-07-19T18:59:22Z Item was in collections: University of Illinois Theses & Dissertations (ID: 1) No. of bitstreams: 1 Miao_Xin.pdf: 2247519 bytes, checksum: 1d94454975d3f21cfc26dc21419fbe9d (MD5)","Made available in DSpace on 2013-08-22T16:38:48Z (GMT). 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