{"id":{"repo_id":"uiuc","oai_identifier":"oai:www.ideals.illinois.edu:2142/42361"},"canonical_url":"https://search.dev.ndltd.org/etd/uiuc/oai:www.ideals.illinois.edu:2142/42361","repository":{"repo_id":"uiuc","name":"University of Illinois - Urbana-Champaign","base_url":"https://www.ideals.illinois.edu/oai-pmh"},"display":{"title":"Using hybrid shared and distributed caching for mixed-coherency GPU workloads","abstract":"Current GPU computing models support a mixture of coherent and incoherent classes of memory operations. Workloads using these models typically have working sets too large to fit in an economical SRAM structure. Still, GPU architectures have last-level caches to primarily fulfill two functions: eliminate redundant DRAM accesses servicing requests from different L1 caches to the same line, and maintain on-chip memory coherence for the coherent class of memory operations. In this thesis, we propose an alternative memory system design for GPU architectures better fit for their workloads. Our architectural design features a directory-like sharing tracker that allows the incoherent private L1 caches to directly satisfy remote requests for shared data. It also retains a shared L2 cache with a customized caching policy to support coherent accesses on-chip and better serve non-coalesced requests that contend aggressively for cache lines. This thesis characterizes the novel and intriguing tradeoffs between the components of our proposed memory system design for area, energy, and performance. We show that the proposed design achieves a 22% average reduction in DRAM data demand over a standard GPU architecture with 1MB L2 cache, leading to an overall 28% reduction in the memory system energy consumption on average. Conversely, our results show that the DRAM data demand of the proposed design with 256KB L2 cache is on par with a standard GPU architecture with 1MB L2 cache, albeit at a smaller area overhead and power leakage. Our results, while drawn on motivations from the GPU realm, are not architecture-specific and can be extended to other throughput-oriented many-core organizations.","abstract_html":"Current GPU computing models support a mixture of coherent and incoherent classes of memory operations. Workloads using these models typically have working sets too large to fit in an economical SRAM structure. Still, GPU architectures have last-level caches to primarily fulfill two functions: eliminate redundant DRAM accesses servicing requests from different L1 caches to the same line, and maintain on-chip memory coherence for the coherent class of memory operations. In this thesis, we propose an alternative memory system design for GPU architectures better fit for their workloads. Our architectural design features a directory-like sharing tracker that allows the incoherent private L1 caches to directly satisfy remote requests for shared data. It also retains a shared L2 cache with a customized caching policy to support coherent accesses on-chip and better serve non-coalesced requests that contend aggressively for cache lines. This thesis characterizes the novel and intriguing tradeoffs between the components of our proposed memory system design for area, energy, and performance. We show that the proposed design achieves a 22% average reduction in DRAM data demand over a standard GPU architecture with 1MB L2 cache, leading to an overall 28% reduction in the memory system energy consumption on average. Conversely, our results show that the DRAM data demand of the proposed design with 256KB L2 cache is on par with a standard GPU architecture with 1MB L2 cache, albeit at a smaller area overhead and power leakage. Our results, while drawn on motivations from the GPU realm, are not architecture-specific and can be extended to other throughput-oriented many-core organizations.","abstract_has_math":false,"creators":["Anssari, Nasser"],"institution":"University of Illinois at Urbana-Champaign","degree_name":"M.S.","degree_level":"Thesis","degree_discipline":"Electrical & Computer Engr","degree_department":null,"school":null,"contributors":["Hwu, Wen-Mei W."],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2013,"date_issued":"2013-02-03T19:36:23Z","date_published":"2013-02-03T19:36:23Z","updated_at":"2026-07-22T22:25:33Z","subjects":["Graphics Processing Unit (GPU) Computing","Cache Coherence","Memory Consistency","Sharing Tracker","High Performance Computing (HPC) Workloads"],"languages":["en"],"rights":["Copyright 2012 Nasser Salim Anssari"],"rights_urls":[],"identifier_entries":[]},"links":{"outbound_url":"http://hdl.handle.net/2142/42361","outbound_label":"Handle","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Hwu, Wen-Mei W."]},{"key":"dc:creator","label":"Author","values":["Anssari, Nasser"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2013-02-03T19:36:23Z","2012-12"]},{"key":"dc:type","label":"Dc Type","values":["text"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Electrical & Computer Engr"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Thesis"]},{"key":"thesis:degree_name","label":"Degree Name","values":["M.S."]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["University of Illinois at Urbana-Champaign"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Graphics Processing Unit (GPU) Computing","Cache Coherence","Memory Consistency","Sharing Tracker","High Performance Computing (HPC) Workloads"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language","label":"Dc Language","values":["en"]},{"key":"dc:rights","label":"Dc Rights","values":["Copyright 2012 Nasser Salim Anssari"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["http://hdl.handle.net/2142/42361"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["Current GPU computing models support a mixture of coherent and incoherent classes of memory operations. Workloads using these models typically have working sets too large to fit in an economical SRAM structure. Still, GPU architectures have last-level caches to primarily fulfill two functions: eliminate redundant DRAM accesses servicing requests from different L1 caches to the same line, and maintain on-chip memory coherence for the coherent class of memory operations. In this thesis, we propose an alternative memory system design for GPU architectures better fit for their workloads. Our architectural design features a directory-like sharing tracker that allows the incoherent private L1 caches to directly satisfy remote requests for shared data. It also retains a shared L2 cache with a customized caching policy to support coherent accesses on-chip and better serve non-coalesced requests that contend aggressively for cache lines. This thesis characterizes the novel and intriguing tradeoffs between the components of our proposed memory system design for area, energy, and performance. We show that the proposed design achieves a 22% average reduction in DRAM data demand over a standard GPU architecture with 1MB L2 cache, leading to an overall 28% reduction in the memory system energy consumption on average. Conversely, our results show that the DRAM data demand of the proposed design with 256KB L2 cache is on par with a standard GPU architecture with 1MB L2 cache, albeit at a smaller area overhead and power leakage. Our results, while drawn on motivations from the GPU realm, are not architecture-specific and can be extended to other throughput-oriented many-core organizations.","Item withdrawn by Mark Zulauf (zulauf@illinois.edu) on 2012-12-05T20:43:41Z Item was in collections: University of Illinois Theses & Dissertations (ID: 1) No. of bitstreams: 2 Anssari_Nasser.zip: 3467706 bytes, checksum: 87221fa4feee1db3d22b6fbc14388bc2 (MD5) Anssari_Nasser.pdf: 1704914 bytes, checksum: c78098241ab29a440f2547763cb625f0 (MD5)","Made available in DSpace on 2013-02-03T19:36:23Z (GMT). No. of bitstreams: 3 Nasser_Anssari.pdf: 1704914 bytes, checksum: c78098241ab29a440f2547763cb625f0 (MD5) Anssari_Nasser.zip: 3467706 bytes, checksum: 87221fa4feee1db3d22b6fbc14388bc2 (MD5) license.txt: 4064 bytes, checksum: ec30af6944980af64ae74e96907ca11b (MD5)"]},{"key":"dc:title","label":"Title","values":["Using hybrid shared and distributed caching for mixed-coherency GPU workloads"]}]}],"canonical_facts":{"dc:contributor":["Hwu, Wen-Mei W."],"dc:creator":["Anssari, Nasser"],"dc:date":["2013-02-03T19:36:23Z","2012-12"],"dc:description":["Current GPU computing models support a mixture of coherent and incoherent classes of memory operations. Workloads using these models typically have working sets too large to fit in an economical SRAM structure. Still, GPU architectures have last-level caches to primarily fulfill two functions: eliminate redundant DRAM accesses servicing requests from different L1 caches to the same line, and maintain on-chip memory coherence for the coherent class of memory operations. In this thesis, we propose an alternative memory system design for GPU architectures better fit for their workloads. Our architectural design features a directory-like sharing tracker that allows the incoherent private L1 caches to directly satisfy remote requests for shared data. It also retains a shared L2 cache with a customized caching policy to support coherent accesses on-chip and better serve non-coalesced requests that contend aggressively for cache lines. This thesis characterizes the novel and intriguing tradeoffs between the components of our proposed memory system design for area, energy, and performance. We show that the proposed design achieves a 22% average reduction in DRAM data demand over a standard GPU architecture with 1MB L2 cache, leading to an overall 28% reduction in the memory system energy consumption on average. Conversely, our results show that the DRAM data demand of the proposed design with 256KB L2 cache is on par with a standard GPU architecture with 1MB L2 cache, albeit at a smaller area overhead and power leakage. Our results, while drawn on motivations from the GPU realm, are not architecture-specific and can be extended to other throughput-oriented many-core organizations.","Item withdrawn by Mark Zulauf (zulauf@illinois.edu) on 2012-12-05T20:43:41Z Item was in collections: University of Illinois Theses & Dissertations (ID: 1) No. of bitstreams: 2 Anssari_Nasser.zip: 3467706 bytes, checksum: 87221fa4feee1db3d22b6fbc14388bc2 (MD5) Anssari_Nasser.pdf: 1704914 bytes, checksum: c78098241ab29a440f2547763cb625f0 (MD5)","Made available in DSpace on 2013-02-03T19:36:23Z (GMT). No. of bitstreams: 3 Nasser_Anssari.pdf: 1704914 bytes, checksum: c78098241ab29a440f2547763cb625f0 (MD5) Anssari_Nasser.zip: 3467706 bytes, checksum: 87221fa4feee1db3d22b6fbc14388bc2 (MD5) license.txt: 4064 bytes, checksum: ec30af6944980af64ae74e96907ca11b (MD5)"],"dc:identifier":["http://hdl.handle.net/2142/42361"],"dc:language":["en"],"dc:rights":["Copyright 2012 Nasser Salim Anssari"],"dc:subject":["Graphics Processing Unit (GPU) Computing","Cache Coherence","Memory Consistency","Sharing Tracker","High Performance Computing (HPC) Workloads"],"dc:title":["Using hybrid shared and distributed caching for mixed-coherency GPU workloads"],"dc:type":["text"],"thesis:degree_discipline":["Electrical & Computer Engr"],"thesis:degree_level":["Thesis"],"thesis:degree_name":["M.S."],"thesis:institution_name":["University of Illinois at Urbana-Champaign"]},"updated_at":"2026-07-22T22:25:33Z"}