{"id":{"repo_id":"uiuc","oai_identifier":"oai:www.ideals.illinois.edu:2142/42360"},"canonical_url":"https://search.dev.ndltd.org/etd/uiuc/oai:www.ideals.illinois.edu:2142/42360","repository":{"repo_id":"uiuc","name":"University of Illinois - Urbana-Champaign","base_url":"https://www.ideals.illinois.edu/oai-pmh"},"display":{"title":"System-level optimization of the DC-DC voltage regulator and core for sub/near-threshold voltage operation","abstract":"Switched capacitor voltage regulator module (SC-VRM) is suitable for low power embedded systems operating in near/sub-threshold region due to its high conversion ratio and compactness. However, existing optimization for SC-VRM is separated from the embedded core design and therefore leads to sub-optimal system energy efficiency. In this thesis, we propose to jointly optimize the switched capacitor voltage regulator module (SC-VRM) and the compute core to minimize system energy per instruction. A core-aware SC-VRM energy model is developed and employed to solve the joint optimization problem. We also propose and optimize a reconfigurable SC-VRM architecture. Simulation results in a 130nm CMOS process indicate that the core-aware SC-VRM model predicts energy from circuit simulations to within 5%, and that the proposed approach results in a maximum system energy savings of 8% to 38.9%. The reconfigurable SC-VRM achieves 15% to 52% energy saving as compared to an efficiency-optimized design.","abstract_html":"Switched capacitor voltage regulator module (SC-VRM) is suitable for low power embedded systems operating in near/sub-threshold region due to its high conversion ratio and compactness. However, existing optimization for SC-VRM is separated from the embedded core design and therefore leads to sub-optimal system energy efficiency. In this thesis, we propose to jointly optimize the switched capacitor voltage regulator module (SC-VRM) and the compute core to minimize system energy per instruction. A core-aware SC-VRM energy model is developed and employed to solve the joint optimization problem. We also propose and optimize a reconfigurable SC-VRM architecture. Simulation results in a 130nm CMOS process indicate that the core-aware SC-VRM model predicts energy from circuit simulations to within 5%, and that the proposed approach results in a maximum system energy savings of 8% to 38.9%. The reconfigurable SC-VRM achieves 15% to 52% energy saving as compared to an efficiency-optimized design.","abstract_has_math":false,"creators":["Zhang, Sai"],"institution":"University of Illinois at Urbana-Champaign","degree_name":"M.S.","degree_level":"Thesis","degree_discipline":"Electrical & Computer Engr","degree_department":null,"school":null,"contributors":["Shanbhag, Naresh R."],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2013,"date_issued":"2013-02-03T19:36:22Z","date_published":"2013-02-03T19:36:22Z","updated_at":"2026-07-22T22:25:33Z","subjects":["Switched capacitor voltage regulator module","Sub/near-threshold operation","Optimization","Low power design"],"languages":["en"],"rights":["Copyright 2012 Sai Zhang"],"rights_urls":[],"identifier_entries":[]},"links":{"outbound_url":"http://hdl.handle.net/2142/42360","outbound_label":"Handle","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Shanbhag, Naresh R."]},{"key":"dc:creator","label":"Author","values":["Zhang, Sai"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2013-02-03T19:36:22Z","2012-12"]},{"key":"dc:type","label":"Dc Type","values":["text"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Electrical & Computer Engr"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Thesis"]},{"key":"thesis:degree_name","label":"Degree Name","values":["M.S."]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["University of Illinois at Urbana-Champaign"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Switched capacitor voltage regulator module","Sub/near-threshold operation","Optimization","Low power design"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language","label":"Dc Language","values":["en"]},{"key":"dc:rights","label":"Dc Rights","values":["Copyright 2012 Sai Zhang"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["http://hdl.handle.net/2142/42360"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["Switched capacitor voltage regulator module (SC-VRM) is suitable for low power embedded systems operating in near/sub-threshold region due to its high conversion ratio and compactness. However, existing optimization for SC-VRM is separated from the embedded core design and therefore leads to sub-optimal system energy efficiency. In this thesis, we propose to jointly optimize the switched capacitor voltage regulator module (SC-VRM) and the compute core to minimize system energy per instruction. A core-aware SC-VRM energy model is developed and employed to solve the joint optimization problem. We also propose and optimize a reconfigurable SC-VRM architecture. Simulation results in a 130nm CMOS process indicate that the core-aware SC-VRM model predicts energy from circuit simulations to within 5%, and that the proposed approach results in a maximum system energy savings of 8% to 38.9%. The reconfigurable SC-VRM achieves 15% to 52% energy saving as compared to an efficiency-optimized design.","Item withdrawn by Mark Zulauf (zulauf@illinois.edu) on 2012-12-11T13:55:15Z Item was in collections: University of Illinois Theses & Dissertations (ID: 1) No. of bitstreams: 1 Zhang_Sai.pdf: 3507355 bytes, checksum: ad2ee5095648a2b4928979867f25f117 (MD5)","Made available in DSpace on 2013-02-03T19:36:22Z (GMT). No. of bitstreams: 2 Sai_Zhang.pdf: 3507355 bytes, checksum: ad2ee5095648a2b4928979867f25f117 (MD5) license.txt: 4059 bytes, checksum: f7fa64eb40d515b3c60adb08482adbec (MD5)"]},{"key":"dc:title","label":"Title","values":["System-level optimization of the DC-DC voltage regulator and core for sub/near-threshold voltage operation"]}]}],"canonical_facts":{"dc:contributor":["Shanbhag, Naresh R."],"dc:creator":["Zhang, Sai"],"dc:date":["2013-02-03T19:36:22Z","2012-12"],"dc:description":["Switched capacitor voltage regulator module (SC-VRM) is suitable for low power embedded systems operating in near/sub-threshold region due to its high conversion ratio and compactness. However, existing optimization for SC-VRM is separated from the embedded core design and therefore leads to sub-optimal system energy efficiency. In this thesis, we propose to jointly optimize the switched capacitor voltage regulator module (SC-VRM) and the compute core to minimize system energy per instruction. A core-aware SC-VRM energy model is developed and employed to solve the joint optimization problem. We also propose and optimize a reconfigurable SC-VRM architecture. Simulation results in a 130nm CMOS process indicate that the core-aware SC-VRM model predicts energy from circuit simulations to within 5%, and that the proposed approach results in a maximum system energy savings of 8% to 38.9%. The reconfigurable SC-VRM achieves 15% to 52% energy saving as compared to an efficiency-optimized design.","Item withdrawn by Mark Zulauf (zulauf@illinois.edu) on 2012-12-11T13:55:15Z Item was in collections: University of Illinois Theses & Dissertations (ID: 1) No. of bitstreams: 1 Zhang_Sai.pdf: 3507355 bytes, checksum: ad2ee5095648a2b4928979867f25f117 (MD5)","Made available in DSpace on 2013-02-03T19:36:22Z (GMT). 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