{"id":{"repo_id":"uiuc","oai_identifier":"oai:www.ideals.illinois.edu:2142/42154"},"canonical_url":"https://search.dev.ndltd.org/etd/uiuc/oai:www.ideals.illinois.edu:2142/42154","repository":{"repo_id":"uiuc","name":"University of Illinois - Urbana-Champaign","base_url":"https://www.ideals.illinois.edu/oai-pmh"},"display":{"title":"Exploring alternatives to hardware support for fine-grain synchronization","abstract":"As we prepare for the extreme-scale era of computing, communication overhead and synchronization between cores will soon become extremely important. In this work we study three different methods of support for fine-grain synchronization. Fine-grain synchronization allows a task to be broken up into very small units, improving load balancing and reducing lock contention. The different methods include hardware support for full/empty bits, compare-and-swap (CAS) emulation of full/empty bits, and dual CAS operations. Roger Golliver’s single CAS implementation is a novel method which chooses a bit pattern to represent an “empty” full/empty bit state. The primary concerns are hardware overhead, efficiency of the synchronization, and energy wasted while spinning. We have tested the methods on a set of four different highly parallel algorithms on up to 32 cores. Our results show that fine-grain synchronization can have significant performance benefits, and emulation through CAS can do just as well as hardware-supported full/empty bits in many cases. We had much difficulty finding suitable algorithms that use fine-grain synchronization in a meaningful way, and among those that did use fine-grain synchronization meaningfully, there were limited cases where hardware support had a significant advantage over emulation through CAS. Given these results, we find it difficult to justify including full/empty bits in an extreme-scale design.","abstract_html":"As we prepare for the extreme-scale era of computing, communication overhead and synchronization between cores will soon become extremely important. In this work we study three different methods of support for fine-grain synchronization. Fine-grain synchronization allows a task to be broken up into very small units, improving load balancing and reducing lock contention. The different methods include hardware support for full/empty bits, compare-and-swap (CAS) emulation of full/empty bits, and dual CAS operations. Roger Golliver’s single CAS implementation is a novel method which chooses a bit pattern to represent an “empty” full/empty bit state. The primary concerns are hardware overhead, efficiency of the synchronization, and energy wasted while spinning. We have tested the methods on a set of four different highly parallel algorithms on up to 32 cores. Our results show that fine-grain synchronization can have significant performance benefits, and emulation through CAS can do just as well as hardware-supported full/empty bits in many cases. We had much difficulty finding suitable algorithms that use fine-grain synchronization in a meaningful way, and among those that did use fine-grain synchronization meaningfully, there were limited cases where hardware support had a significant advantage over emulation through CAS. Given these results, we find it difficult to justify including full/empty bits in an extreme-scale design.","abstract_has_math":false,"creators":["Ahrens, Benjamin"],"institution":"University of Illinois at Urbana-Champaign","degree_name":"M.S.","degree_level":"Thesis","degree_discipline":"Electrical & Computer Engr","degree_department":null,"school":null,"contributors":["Torrellas, Josep"],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2013,"date_issued":"2013-02-03T19:17:39Z","date_published":"2013-02-03T19:17:39Z","updated_at":"2026-07-22T22:25:31Z","subjects":["fine-grain synchronization","compare-and-swap","full/empty bits"],"languages":["en"],"rights":["Copyright 2012 Benjamin Ahrens"],"rights_urls":[],"identifier_entries":[]},"links":{"outbound_url":"http://hdl.handle.net/2142/42154","outbound_label":"Handle","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Torrellas, Josep"]},{"key":"dc:creator","label":"Author","values":["Ahrens, Benjamin"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2013-02-03T19:17:39Z","2015-02-03T11:00:59Z","2012-12"]},{"key":"dc:type","label":"Dc Type","values":["text"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Electrical & Computer Engr"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Thesis"]},{"key":"thesis:degree_name","label":"Degree Name","values":["M.S."]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["University of Illinois at Urbana-Champaign"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["fine-grain synchronization","compare-and-swap","full/empty bits"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language","label":"Dc Language","values":["en"]},{"key":"dc:rights","label":"Dc Rights","values":["Copyright 2012 Benjamin Ahrens"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["http://hdl.handle.net/2142/42154"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["As we prepare for the extreme-scale era of computing, communication overhead and synchronization between cores will soon become extremely important. In this work we study three different methods of support for fine-grain synchronization. Fine-grain synchronization allows a task to be broken up into very small units, improving load balancing and reducing lock contention. The different methods include hardware support for full/empty bits, compare-and-swap (CAS) emulation of full/empty bits, and dual CAS operations. Roger Golliver’s single CAS implementation is a novel method which chooses a bit pattern to represent an “empty” full/empty bit state. The primary concerns are hardware overhead, efficiency of the synchronization, and energy wasted while spinning. We have tested the methods on a set of four different highly parallel algorithms on up to 32 cores. Our results show that fine-grain synchronization can have significant performance benefits, and emulation through CAS can do just as well as hardware-supported full/empty bits in many cases. We had much difficulty finding suitable algorithms that use fine-grain synchronization in a meaningful way, and among those that did use fine-grain synchronization meaningfully, there were limited cases where hardware support had a significant advantage over emulation through CAS. Given these results, we find it difficult to justify including full/empty bits in an extreme-scale design.","Item withdrawn by Mark Zulauf (zulauf@illinois.edu) on 2012-12-10T21:17:21Z Item was in collections: University of Illinois Theses & Dissertations (ID: 1) No. of bitstreams: 1 Ahrens_Benjamin.pdf: 410618 bytes, checksum: 54a10f2c52a1619d634022bc888219e6 (MD5)","Made available in DSpace on 2013-02-03T19:17:39Z (GMT). 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In this work we study three different methods of support for fine-grain synchronization. Fine-grain synchronization allows a task to be broken up into very small units, improving load balancing and reducing lock contention. The different methods include hardware support for full/empty bits, compare-and-swap (CAS) emulation of full/empty bits, and dual CAS operations. Roger Golliver’s single CAS implementation is a novel method which chooses a bit pattern to represent an “empty” full/empty bit state. The primary concerns are hardware overhead, efficiency of the synchronization, and energy wasted while spinning. We have tested the methods on a set of four different highly parallel algorithms on up to 32 cores. Our results show that fine-grain synchronization can have significant performance benefits, and emulation through CAS can do just as well as hardware-supported full/empty bits in many cases. We had much difficulty finding suitable algorithms that use fine-grain synchronization in a meaningful way, and among those that did use fine-grain synchronization meaningfully, there were limited cases where hardware support had a significant advantage over emulation through CAS. Given these results, we find it difficult to justify including full/empty bits in an extreme-scale design.","Item withdrawn by Mark Zulauf (zulauf@illinois.edu) on 2012-12-10T21:17:21Z Item was in collections: University of Illinois Theses & Dissertations (ID: 1) No. of bitstreams: 1 Ahrens_Benjamin.pdf: 410618 bytes, checksum: 54a10f2c52a1619d634022bc888219e6 (MD5)","Made available in DSpace on 2013-02-03T19:17:39Z (GMT). No. of bitstreams: 2 Benjamin_Ahrens.pdf: 410618 bytes, checksum: 54a10f2c52a1619d634022bc888219e6 (MD5) license.txt: 4065 bytes, checksum: 16f710cff9acf4278dd4523ae738bc13 (MD5)","Item marked as restricted to the 'UIUC Users [automated]' Group (id=2) by Seth Robbins (srobbins@illinois.edu) on 2013-02-03T19:19:03Z Item is restricted until 2015-02-03T19:18:53Z","Restriction data tranferred 2014-07-01T11:11:56-05:00 Original Data Group with Access UIUC Users [automated] Release Date: 2015-02-03 13:18:53 UTC Reason: Author requested U of Illinois access only (OA after 2yrs) in Vireo ETD system","U of I Only Restriction Lifted for Item 42101 on 2015-02-03T11:00:59Z."],"dc:identifier":["http://hdl.handle.net/2142/42154"],"dc:language":["en"],"dc:rights":["Copyright 2012 Benjamin Ahrens"],"dc:subject":["fine-grain synchronization","compare-and-swap","full/empty bits"],"dc:title":["Exploring alternatives to hardware support for fine-grain synchronization"],"dc:type":["text"],"thesis:degree_discipline":["Electrical & Computer Engr"],"thesis:degree_level":["Thesis"],"thesis:degree_name":["M.S."],"thesis:institution_name":["University of Illinois at Urbana-Champaign"]},"updated_at":"2026-07-22T22:25:31Z"}