{"id":{"repo_id":"uiuc","oai_identifier":"oai:www.ideals.illinois.edu:2142/34585"},"canonical_url":"https://search.dev.ndltd.org/etd/uiuc/oai:www.ideals.illinois.edu:2142/34585","repository":{"repo_id":"uiuc","name":"University of Illinois - Urbana-Champaign","base_url":"https://www.ideals.illinois.edu/oai-pmh"},"display":{"title":"Refrint: intelligent refresh to minimize power in on-chip multiprocessor cache hierarchies","abstract":"As manycores use dynamic energy ever more efficiently, static power consumption becomes a major concern. In particular, in a large manycore running at a low voltage, leakage in on-chip memory modules contributes substantially to the chip’s power draw. This is unfortunate given that, intuitively, the large multi-level cache hierarchy of a manycore is likely to contain a lot of useless data. An effective way to reduce this problem is to use a low-leakage technology such as embedded DRAM (eDRAM). However, such systems require refresh. In this paper, we examine the opportunity of minimizing on-chip memory power by intelligently refreshing a full-eDRAM cache hierarchy. We present Refrint, a simple approach to perform fine-grained, intelligent refresh of eDRAM multiprocessor cache hierarchies. We introduce the Refrint algorithms and the microarchitecture support. We evaluate Refrint in a simulated manycore running 16-threaded parallel applications. Compared to a full-SRAM system, Refrint’s memory hierarchy only consumes 36% of the SRAM’s memory hierarchy energy and induces a negligible slowdown. In contrast, a basic full-eDRAM memory hierarchy consumes 50% of the SRAM’s memory hierarchy energy and induces a slowdown of 18%.","abstract_html":"As manycores use dynamic energy ever more efficiently, static power consumption becomes a major concern. In particular, in a large manycore running at a low voltage, leakage in on-chip memory modules contributes substantially to the chip’s power draw. This is unfortunate given that, intuitively, the large multi-level cache hierarchy of a manycore is likely to contain a lot of useless data. An effective way to reduce this problem is to use a low-leakage technology such as embedded DRAM (eDRAM). However, such systems require refresh. In this paper, we examine the opportunity of minimizing on-chip memory power by intelligently refreshing a full-eDRAM cache hierarchy. We present Refrint, a simple approach to perform fine-grained, intelligent refresh of eDRAM multiprocessor cache hierarchies. We introduce the Refrint algorithms and the microarchitecture support. We evaluate Refrint in a simulated manycore running 16-threaded parallel applications. Compared to a full-SRAM system, Refrint’s memory hierarchy only consumes 36% of the SRAM’s memory hierarchy energy and induces a negligible slowdown. In contrast, a basic full-eDRAM memory hierarchy consumes 50% of the SRAM’s memory hierarchy energy and induces a slowdown of 18%.","abstract_has_math":false,"creators":["Jain, Prabhat"],"institution":"University of Illinois at Urbana-Champaign","degree_name":"M.S.","degree_level":"Thesis","degree_discipline":"Computer Science","degree_department":null,"school":null,"contributors":["Torrellas, Josep"],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2012,"date_issued":"2012-09-18T21:26:44Z","date_published":"2012-09-18T21:26:44Z","updated_at":"2026-07-22T22:25:31Z","subjects":["Static random-access memory (SRAM)","Embedded dynamic random-access memory (eDRAM)","memory hierarchy","computer architecture","leakage","refresh power"],"languages":["en"],"rights":["Copyright 2012 Prabhat Jain"],"rights_urls":[],"identifier_entries":[]},"links":{"outbound_url":"http://hdl.handle.net/2142/34585","outbound_label":"Handle","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Torrellas, Josep"]},{"key":"dc:creator","label":"Author","values":["Jain, Prabhat"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2012-09-18T21:26:44Z","2014-09-18T10:00:47Z","2012-08"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Computer Science"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Thesis"]},{"key":"thesis:degree_name","label":"Degree Name","values":["M.S."]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["University of Illinois at Urbana-Champaign"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Static random-access memory (SRAM)","Embedded dynamic random-access memory (eDRAM)","memory hierarchy","computer architecture","leakage","refresh power"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language","label":"Dc Language","values":["en"]},{"key":"dc:rights","label":"Dc Rights","values":["Copyright 2012 Prabhat Jain"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["http://hdl.handle.net/2142/34585"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["As manycores use dynamic energy ever more efficiently, static power consumption becomes a major concern. In particular, in a large manycore running at a low voltage, leakage in on-chip memory modules contributes substantially to the chip’s power draw. This is unfortunate given that, intuitively, the large multi-level cache hierarchy of a manycore is likely to contain a lot of useless data. An effective way to reduce this problem is to use a low-leakage technology such as embedded DRAM (eDRAM). However, such systems require refresh. In this paper, we examine the opportunity of minimizing on-chip memory power by intelligently refreshing a full-eDRAM cache hierarchy. We present Refrint, a simple approach to perform fine-grained, intelligent refresh of eDRAM multiprocessor cache hierarchies. We introduce the Refrint algorithms and the microarchitecture support. We evaluate Refrint in a simulated manycore running 16-threaded parallel applications. Compared to a full-SRAM system, Refrint’s memory hierarchy only consumes 36% of the SRAM’s memory hierarchy energy and induces a negligible slowdown. In contrast, a basic full-eDRAM memory hierarchy consumes 50% of the SRAM’s memory hierarchy energy and induces a slowdown of 18%.","Item withdrawn by Mark Zulauf (zulauf@illinois.edu) on 2012-06-26T13:56:30Z Item was in collections: University of Illinois Theses & Dissertations (ID: 1) No. of bitstreams: 1 Jain_Prabhat.pdf: 355209 bytes, checksum: ef80450a373f000c9166985536a835f4 (MD5)","Made available in DSpace on 2012-09-18T21:26:44Z (GMT). No. of bitstreams: 2 Jain_Prabhat.pdf: 355210 bytes, checksum: 6b3a29b6cfadd289965c035e7ce2b153 (MD5) license.txt: 4060 bytes, checksum: bbd0e2d932eaec1d0ebeb3f95275ef68 (MD5)","Item marked as restricted to the 'Administrator' Group (id=1) by Seth Robbins (srobbins@illinois.edu) on 2012-09-18T21:27:37Z Item is restricted until 2014-09-18T21:27:16Z","Restriction data tranferred 2014-07-01T11:35:55-05:00 Original Data Group with Access Administrator Release Date: 2014-09-18 16:27:16 UTC Reason: Author requested closed access (OA after 2yrs) in Vireo ETD system","Limited Restriction Lifted for Item 34859 on 2014-09-18T10:00:47Z."]},{"key":"dc:title","label":"Title","values":["Refrint: intelligent refresh to minimize power in on-chip multiprocessor cache hierarchies"]}]}],"canonical_facts":{"dc:contributor":["Torrellas, Josep"],"dc:creator":["Jain, Prabhat"],"dc:date":["2012-09-18T21:26:44Z","2014-09-18T10:00:47Z","2012-08"],"dc:description":["As manycores use dynamic energy ever more efficiently, static power consumption becomes a major concern. In particular, in a large manycore running at a low voltage, leakage in on-chip memory modules contributes substantially to the chip’s power draw. This is unfortunate given that, intuitively, the large multi-level cache hierarchy of a manycore is likely to contain a lot of useless data. An effective way to reduce this problem is to use a low-leakage technology such as embedded DRAM (eDRAM). However, such systems require refresh. In this paper, we examine the opportunity of minimizing on-chip memory power by intelligently refreshing a full-eDRAM cache hierarchy. We present Refrint, a simple approach to perform fine-grained, intelligent refresh of eDRAM multiprocessor cache hierarchies. We introduce the Refrint algorithms and the microarchitecture support. We evaluate Refrint in a simulated manycore running 16-threaded parallel applications. Compared to a full-SRAM system, Refrint’s memory hierarchy only consumes 36% of the SRAM’s memory hierarchy energy and induces a negligible slowdown. In contrast, a basic full-eDRAM memory hierarchy consumes 50% of the SRAM’s memory hierarchy energy and induces a slowdown of 18%.","Item withdrawn by Mark Zulauf (zulauf@illinois.edu) on 2012-06-26T13:56:30Z Item was in collections: University of Illinois Theses & Dissertations (ID: 1) No. of bitstreams: 1 Jain_Prabhat.pdf: 355209 bytes, checksum: ef80450a373f000c9166985536a835f4 (MD5)","Made available in DSpace on 2012-09-18T21:26:44Z (GMT). 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