{"id":{"repo_id":"uiuc","oai_identifier":"oai:www.ideals.illinois.edu:2142/29565"},"canonical_url":"https://search.dev.ndltd.org/etd/uiuc/oai:www.ideals.illinois.edu:2142/29565","repository":{"repo_id":"uiuc","name":"University of Illinois - Urbana-Champaign","base_url":"https://www.ideals.illinois.edu/oai-pmh"},"display":{"title":"SHA-less pipeline ADC design with sampling clock skew calibration","abstract":"The power efficiency of pipeline analog-to-digital converters (ADCs) can be substantially improved by eliminating the front-end sample-and-hold amplifier (SHA). However, in a SHA-less architecture the sampling clock skew between the sub-ADC and the multiplying digital-to-analog converter (MDAC) in the pipeline first stage results in gross conversion errors at high input frequencies. This skew effect is aggravated in a SHA-less multi-bit-per-stage pipeline architecture, where the built-in redundancy is limited. Sampling clock skew is an essential problem in SHA-less pipeline ADCs that prohibits their use at high input frequency applications. In this thesis, a mostly digital background calibration technique is developed to remove the sampling clock skew in SHA-less pipeline ADCs. The skew information is extracted from the first-stage residue output with two comparators sensing out-of-range errors; a gradient-descent algorithm is used to adaptively adjust the timing of the sub-ADC to synchronize with that of the sample-and-hold (S/H) in the MDAC. A prototype 10-bit, 100-MS/s SHA-less pipeline ADC incorporating this calibration technique was designed and fabricated in 90-nm CMOS process. The prototype ADC converts from DC to the 12th Nyquist band with a 3.5-bit front-end stage. It digitizes inputs up to 610 MHz without skew errors in experiments; in contrast, the same ADC fails at 130 MHz with calibration disabled. The calibration circuits were fully integrated on chip. The ADC consumes 12.2 mW and occupies 0.26-mm2 silicon area, while the calibration circuits dissipate 0.9 mW and occupy 0.01 mm2. A 71-dB spurious-free dynamic range (SFDR) and a 55-dB signal-to-noise-and-distortion ratio (SNDR) were measured with a 20-MHz sine-wave input, and a larger than 55-dB SFDR was measured in the 10th Nyquist band.","abstract_html":"The power efficiency of pipeline analog-to-digital converters (ADCs) can be substantially improved by eliminating the front-end sample-and-hold amplifier (SHA). However, in a SHA-less architecture the sampling clock skew between the sub-ADC and the multiplying digital-to-analog converter (MDAC) in the pipeline first stage results in gross conversion errors at high input frequencies. This skew effect is aggravated in a SHA-less multi-bit-per-stage pipeline architecture, where the built-in redundancy is limited. Sampling clock skew is an essential problem in SHA-less pipeline ADCs that prohibits their use at high input frequency applications. In this thesis, a mostly digital background calibration technique is developed to remove the sampling clock skew in SHA-less pipeline ADCs. The skew information is extracted from the first-stage residue output with two comparators sensing out-of-range errors; a gradient-descent algorithm is used to adaptively adjust the timing of the sub-ADC to synchronize with that of the sample-and-hold (S/H) in the MDAC. A prototype 10-bit, 100-MS/s SHA-less pipeline ADC incorporating this calibration technique was designed and fabricated in 90-nm CMOS process. The prototype ADC converts from DC to the 12th Nyquist band with a 3.5-bit front-end stage. It digitizes inputs up to 610 MHz without skew errors in experiments; in contrast, the same ADC fails at 130 MHz with calibration disabled. The calibration circuits were fully integrated on chip. The ADC consumes 12.2 mW and occupies 0.26-mm2 silicon area, while the calibration circuits dissipate 0.9 mW and occupy 0.01 mm2. A 71-dB spurious-free dynamic range (SFDR) and a 55-dB signal-to-noise-and-distortion ratio (SNDR) were measured with a 20-MHz sine-wave input, and a larger than 55-dB SFDR was measured in the 10th Nyquist band.","abstract_has_math":false,"creators":["Huang, Pingli"],"institution":"University of Illinois at Urbana-Champaign","degree_name":"Ph.D.","degree_level":"Dissertation","degree_discipline":"Electrical & Computer Engr","degree_department":null,"school":null,"contributors":["Chiu, Yun","Feng, Milton","Rosenbaum, Elyse","Wong, Martin D.F."],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2012,"date_issued":"2012-02-01T00:55:42Z","date_published":"2012-02-01T00:55:42Z","updated_at":"2026-07-22T22:25:27Z","subjects":["Sample-and-hold amplifier (SHA)","SHA-less","pipelined ADC","multi-bit pipeline architecture","sampling clock skew","skew calibration.","analog-to-digital converters (ADCs)"],"languages":["en"],"rights":["COPYRIGHT 2011 PINGLI HUANG"],"rights_urls":[],"identifier_entries":[]},"links":{"outbound_url":"http://hdl.handle.net/2142/29565","outbound_label":"Handle","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Chiu, Yun","Feng, Milton","Rosenbaum, Elyse","Wong, Martin D.F."]},{"key":"dc:creator","label":"Author","values":["Huang, Pingli"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2012-02-01T00:55:42Z","2014-02-01T11:00:34Z","2011-12"]},{"key":"dc:type","label":"Dc Type","values":["Dissertation / Thesis","text"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Electrical & Computer Engr"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Dissertation"]},{"key":"thesis:degree_name","label":"Degree Name","values":["Ph.D."]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["University of Illinois at Urbana-Champaign"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Sample-and-hold amplifier (SHA)","SHA-less","pipelined ADC","multi-bit pipeline architecture","sampling clock skew","skew calibration.","analog-to-digital converters (ADCs)"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language","label":"Dc Language","values":["en"]},{"key":"dc:rights","label":"Dc Rights","values":["COPYRIGHT 2011 PINGLI HUANG"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["http://hdl.handle.net/2142/29565"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["The power efficiency of pipeline analog-to-digital converters (ADCs) can be substantially improved by eliminating the front-end sample-and-hold amplifier (SHA). However, in a SHA-less architecture the sampling clock skew between the sub-ADC and the multiplying digital-to-analog converter (MDAC) in the pipeline first stage results in gross conversion errors at high input frequencies. This skew effect is aggravated in a SHA-less multi-bit-per-stage pipeline architecture, where the built-in redundancy is limited. Sampling clock skew is an essential problem in SHA-less pipeline ADCs that prohibits their use at high input frequency applications. In this thesis, a mostly digital background calibration technique is developed to remove the sampling clock skew in SHA-less pipeline ADCs. The skew information is extracted from the first-stage residue output with two comparators sensing out-of-range errors; a gradient-descent algorithm is used to adaptively adjust the timing of the sub-ADC to synchronize with that of the sample-and-hold (S/H) in the MDAC. A prototype 10-bit, 100-MS/s SHA-less pipeline ADC incorporating this calibration technique was designed and fabricated in 90-nm CMOS process. The prototype ADC converts from DC to the 12th Nyquist band with a 3.5-bit front-end stage. It digitizes inputs up to 610 MHz without skew errors in experiments; in contrast, the same ADC fails at 130 MHz with calibration disabled. The calibration circuits were fully integrated on chip. The ADC consumes 12.2 mW and occupies 0.26-mm2 silicon area, while the calibration circuits dissipate 0.9 mW and occupy 0.01 mm2. A 71-dB spurious-free dynamic range (SFDR) and a 55-dB signal-to-noise-and-distortion ratio (SNDR) were measured with a 20-MHz sine-wave input, and a larger than 55-dB SFDR was measured in the 10th Nyquist band.","Item withdrawn by Mark Zulauf (zulauf@illinois.edu) on 2011-11-30T15:14:49Z Item was in collections: University of Illinois Theses & Dissertations (ID: 1) No. of bitstreams: 1 Huang_pingli.pdf.pdf: 2178723 bytes, checksum: 20c8c4e96af5d526352901f6c94832aa (MD5)","Made available in DSpace on 2012-02-01T00:55:42Z (GMT). No. of bitstreams: 2 Huang_Pingli.pdf: 2178723 bytes, checksum: 20c8c4e96af5d526352901f6c94832aa (MD5) license.txt: 4061 bytes, checksum: 6525e31afc3ee226d93337f16448e959 (MD5)","Item marked as restricted to the 'Administrator' Group (id=1) by William Ingram (wingram2@illinois.edu) on 2012-02-01T00:57:20Z Item is restricted until 2014-02-01T00:56:58Z","Item reinstated by Sarah Shreeves (sshreeve@illinois.edu) on 2014-02-01T11:00:34Z Item was in collections: Graduate Theses and Dissertations at Illinois (ID: 204) Dissertations and Theses - Electrical and Computer Engineering (ID: 446) No. of bitstreams: 3 Huang_Pingli.pdf.txt: 150710 bytes, checksum: 29f3378947bbe5cfa65d0baf11f92c21 (MD5) Huang_Pingli.pdf: 2178723 bytes, checksum: 20c8c4e96af5d526352901f6c94832aa (MD5) license.txt: 4061 bytes, checksum: 6525e31afc3ee226d93337f16448e959 (MD5)","Item released from any restrictions by Sarah Shreeves (sshreeve@illinois.edu) on 2014-02-01T11:00:34Z"]},{"key":"dc:title","label":"Title","values":["SHA-less pipeline ADC design with sampling clock skew calibration"]}]}],"canonical_facts":{"dc:contributor":["Chiu, Yun","Feng, Milton","Rosenbaum, Elyse","Wong, Martin D.F."],"dc:creator":["Huang, Pingli"],"dc:date":["2012-02-01T00:55:42Z","2014-02-01T11:00:34Z","2011-12"],"dc:description":["The power efficiency of pipeline analog-to-digital converters (ADCs) can be substantially improved by eliminating the front-end sample-and-hold amplifier (SHA). However, in a SHA-less architecture the sampling clock skew between the sub-ADC and the multiplying digital-to-analog converter (MDAC) in the pipeline first stage results in gross conversion errors at high input frequencies. This skew effect is aggravated in a SHA-less multi-bit-per-stage pipeline architecture, where the built-in redundancy is limited. Sampling clock skew is an essential problem in SHA-less pipeline ADCs that prohibits their use at high input frequency applications. In this thesis, a mostly digital background calibration technique is developed to remove the sampling clock skew in SHA-less pipeline ADCs. The skew information is extracted from the first-stage residue output with two comparators sensing out-of-range errors; a gradient-descent algorithm is used to adaptively adjust the timing of the sub-ADC to synchronize with that of the sample-and-hold (S/H) in the MDAC. A prototype 10-bit, 100-MS/s SHA-less pipeline ADC incorporating this calibration technique was designed and fabricated in 90-nm CMOS process. The prototype ADC converts from DC to the 12th Nyquist band with a 3.5-bit front-end stage. It digitizes inputs up to 610 MHz without skew errors in experiments; in contrast, the same ADC fails at 130 MHz with calibration disabled. The calibration circuits were fully integrated on chip. The ADC consumes 12.2 mW and occupies 0.26-mm2 silicon area, while the calibration circuits dissipate 0.9 mW and occupy 0.01 mm2. A 71-dB spurious-free dynamic range (SFDR) and a 55-dB signal-to-noise-and-distortion ratio (SNDR) were measured with a 20-MHz sine-wave input, and a larger than 55-dB SFDR was measured in the 10th Nyquist band.","Item withdrawn by Mark Zulauf (zulauf@illinois.edu) on 2011-11-30T15:14:49Z Item was in collections: University of Illinois Theses & Dissertations (ID: 1) No. of bitstreams: 1 Huang_pingli.pdf.pdf: 2178723 bytes, checksum: 20c8c4e96af5d526352901f6c94832aa (MD5)","Made available in DSpace on 2012-02-01T00:55:42Z (GMT). No. of bitstreams: 2 Huang_Pingli.pdf: 2178723 bytes, checksum: 20c8c4e96af5d526352901f6c94832aa (MD5) license.txt: 4061 bytes, checksum: 6525e31afc3ee226d93337f16448e959 (MD5)","Item marked as restricted to the 'Administrator' Group (id=1) by William Ingram (wingram2@illinois.edu) on 2012-02-01T00:57:20Z Item is restricted until 2014-02-01T00:56:58Z","Item reinstated by Sarah Shreeves (sshreeve@illinois.edu) on 2014-02-01T11:00:34Z Item was in collections: Graduate Theses and Dissertations at Illinois (ID: 204) Dissertations and Theses - Electrical and Computer Engineering (ID: 446) No. of bitstreams: 3 Huang_Pingli.pdf.txt: 150710 bytes, checksum: 29f3378947bbe5cfa65d0baf11f92c21 (MD5) Huang_Pingli.pdf: 2178723 bytes, checksum: 20c8c4e96af5d526352901f6c94832aa (MD5) license.txt: 4061 bytes, checksum: 6525e31afc3ee226d93337f16448e959 (MD5)","Item released from any restrictions by Sarah Shreeves (sshreeve@illinois.edu) on 2014-02-01T11:00:34Z"],"dc:identifier":["http://hdl.handle.net/2142/29565"],"dc:language":["en"],"dc:rights":["COPYRIGHT 2011 PINGLI HUANG"],"dc:subject":["Sample-and-hold amplifier (SHA)","SHA-less","pipelined ADC","multi-bit pipeline architecture","sampling clock skew","skew calibration.","analog-to-digital converters (ADCs)"],"dc:title":["SHA-less pipeline ADC design with sampling clock skew calibration"],"dc:type":["Dissertation / Thesis","text"],"thesis:degree_discipline":["Electrical & Computer Engr"],"thesis:degree_level":["Dissertation"],"thesis:degree_name":["Ph.D."],"thesis:institution_name":["University of Illinois at Urbana-Champaign"]},"updated_at":"2026-07-22T22:25:27Z"}