System-Aware Design of Energy-Efficient High-Speed I/O Links
type: CreativeWork
description: Today's high-speed I/O links operate under stringent specifications: few tens of Gb/s data rates over 20 inches of copper trace, power efficiencies of the order of 10-to-30 mW/Gb/s and a bit error-rate (BER) target of 10^(-12) or lower. State-of-the-art I/O links consist of a transmit driver, PLL, equalizer, clock recovery unit and comparator, primarily implemented with mixed-signal components, to achieve the desired BER without forward error correction (FEC). More recently, analog-to-digital converter (ADC) based receivers have gained acceptance owing to the advantages of digital-intensive designs, viz., their propensity to bene fit from technology scaling and Moore's law. In this thesis, we propose a system-assisted mixed-signal (SAMS) design approach, wherein mixed-signal components of a communication link are designed to meet a system-level performance metric such as BER, in contrast to the component-level design techniques prevalent today. First, we propose FEC-assisted I/O link design, where the FEC coding-gain is leveraged to relax the specifi cations of the mixed-signal components of such links, and achieve improved energy-efficiency. In particular, we demonstrate that FEC coding gain can be leveraged to achieve improvements in transmit driver swing, ADC precision, timing jitter and comparator off set specifi cations necessary to meet the link BER specifi cation. We demonstrate that through a combination of coding and modulation, improvements in link energy-efficiency can be achieved. We propose binary BCH codes, as these codes o ffer sufficient coding gain at moderate to high code-rates, and can be implemented at low power via techniques presented in this thesis. Further, we propose an accurate statistical model to evaluate the impact of FEC on DFE-based links, and employ this model to evaluate random and burst error-correcting binary BCH codes. This is necessary to evaluate FEC performance at the low error rates of interest, where simulations are not feasi…
abstract: Today's high-speed I/O links operate under stringent specifications: few tens of Gb/s data rates over 20 inches of copper trace, power efficiencies of the order of 10-to-30 mW/Gb/s and a bit error-rate (BER) target of 10^(-12) or lower. State-of-the-art I/O links consist of a transmit driver, PLL, equalizer, clock recovery unit and comparator, primarily implemented with mixed-signal components, to achieve the desired BER without forward error correction (FEC). More recently, analog-to-digital converter (ADC) based receivers have gained acceptance owing to the advantages of digital-intensive designs, viz., their propensity to bene fit from technology scaling and Moore's law. In this thesis, we propose a system-assisted mixed-signal (SAMS) design approach, wherein mixed-signal components of a communication link are designed to meet a system-level performance metric such as BER, in contrast to the component-level design techniques prevalent today. First, we propose FEC-assisted I/O link design, where the FEC coding-gain is leveraged to relax the specifi cations of the mixed-signal components of such links, and achieve improved energy-efficiency. In particular, we demonstrate that FEC coding gain can be leveraged to achieve improvements in transmit driver swing, ADC precision, timing jitter and comparator off set specifi cations necessary to meet the link BER specifi cation. We demonstrate that through a combination of coding and modulation, improvements in link energy-efficiency can be achieved. We propose binary BCH codes, as these codes o ffer sufficient coding gain at moderate to high code-rates, and can be implemented at low power via techniques presented in this thesis. Further, we propose an accurate statistical model to evaluate the impact of FEC on DFE-based links, and employ this model to evaluate random and burst error-correcting binary BCH codes. This is necessary to evaluate FEC performance at the low error rates of interest, where simulations are not feasi…
author: Lakshmi Narasimha, Rajan
language: en
keywords: energy-efficiency, high-speed link, forward error correction, analog-to-digital converters, bit error rate
date published: 2011-08-25T22:19:19Z
date modified: 2026-07-22T22:25:26Z
provider: University of Illinois - Urbana-Champaign
publisher: Networked Digital Library of Theses and Dissertations
type: WebPage
source organization: University of Illinois at Urbana-Champaign

PropertyValue
property ID: Handle
value: http://hdl.handle.net/2142/26220