{"id":{"repo_id":"uiuc","oai_identifier":"oai:www.ideals.illinois.edu:2142/23128"},"canonical_url":"https://search.dev.ndltd.org/etd/uiuc/oai:www.ideals.illinois.edu:2142/23128","repository":{"repo_id":"uiuc","name":"University of Illinois - Urbana-Champaign","base_url":"https://www.ideals.illinois.edu/oai-pmh"},"display":{"title":"Reducing memory access delays in large-scale shared-memory multiprocessors","abstract":"Memory access time is a key factor limiting the performance of large-scale, shared-memory multiprocessors. In such systems, limited bandwidth in the interconnection between the processors and the memories, coupled with long delays resulting from network and memory conflicts, can produce serious memory access delays. Incorporating memory hierarchies and asynchronous block transfer mechanisms are common methods for reducing these delays. However, for these two mechanisms to be wed advantageously, they must be managed effectively, either in hardware or in software. Although this memory management problem is becoming increasingly important, good techniques are still lacking.","abstract_html":"Memory access time is a key factor limiting the performance of large-scale, shared-memory multiprocessors. In such systems, limited bandwidth in the interconnection between the processors and the memories, coupled with long delays resulting from network and memory conflicts, can produce serious memory access delays. Incorporating memory hierarchies and asynchronous block transfer mechanisms are common methods for reducing these delays. However, for these two mechanisms to be wed advantageously, they must be managed effectively, either in hardware or in software. Although this memory management problem is becoming increasingly important, good techniques are still lacking.","abstract_has_math":false,"creators":["Granston, Elana Denise"],"institution":"University of Illinois at Urbana-Champaign","degree_name":"Ph.D.","degree_level":"Dissertation","degree_discipline":"Computer Science","degree_department":null,"school":null,"contributors":["Veidenbaum, Alexander V."],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2011,"date_issued":"2011-05-07T14:03:10Z","date_published":"2011-05-07T14:03:10Z","updated_at":"2026-07-22T22:25:21Z","subjects":["Computer Science"],"languages":["eng"],"rights":["Copyright 1992 Granston, Elana Denise"],"rights_urls":[],"identifier_entries":[{"key":"dc:identifier","label":"Identifier","values":["AAI9305540","(UMI)AAI9305540"],"render_values":[{"text":"AAI9305540","href":null,"code":true},{"text":"(UMI)AAI9305540","href":null,"code":true}]}]},"links":{"outbound_url":"http://hdl.handle.net/2142/23128","outbound_label":"Handle","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Veidenbaum, Alexander V."]},{"key":"dc:creator","label":"Author","values":["Granston, Elana Denise"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2011-05-07T14:03:10Z","10000-01-01","1992"]},{"key":"dc:type","label":"Dc Type","values":["text"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Computer Science"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Dissertation"]},{"key":"thesis:degree_name","label":"Degree Name","values":["Ph.D."]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["University of Illinois at Urbana-Champaign"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Computer Science"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language","label":"Dc Language","values":["eng"]},{"key":"dc:rights","label":"Dc Rights","values":["Copyright 1992 Granston, Elana Denise"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["AAI9305540","(UMI)AAI9305540","http://hdl.handle.net/2142/23128"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["Memory access time is a key factor limiting the performance of large-scale, shared-memory multiprocessors. In such systems, limited bandwidth in the interconnection between the processors and the memories, coupled with long delays resulting from network and memory conflicts, can produce serious memory access delays. Incorporating memory hierarchies and asynchronous block transfer mechanisms are common methods for reducing these delays. However, for these two mechanisms to be wed advantageously, they must be managed effectively, either in hardware or in software. Although this memory management problem is becoming increasingly important, good techniques are still lacking.","The problem of reducing memory access delays can be attacked at several levels. The first is to attempt to improve the performance of the shared-memory system itself, where the shared-memory system includes implicitly both the network and the memory modules themselves. The second is to develop techniques to manage the memory hierarchy more effectively and to make use of the block transfer mechanisms.","This thesis addresses this problem at both of these levels. The first part examines the behavior of a realistic shared-memory system and evaluates cost-effective hardware modifications for improving this balance. An additional goal is to achieve memory system scalability, where the term scalable describes systems whose per-processor performance is roughly constant across the range of system sizes examined.","The remainder of this thesis addresses the problem of improving utilization of local storage in shared-memory systems where, at the very least, each processor has access to local (private) storage in addition to the global (shared) memory. A combined flow-and-dependence analysis algorithm is developed which produces the analytical information needed to optimize data accesses. It is shown how this information can be used as part of an intergrated hardware/software approach to eliminating redundant (unnecessary) memory accesses and prefetching data.","Made available in DSpace on 2011-05-07T14:03:10Z (GMT). No. of bitstreams: 2 license.txt: 4922 bytes, checksum: 910b249b4beec47e7ab768910c8f966f (MD5) 9305540.pdf: 5060491 bytes, checksum: fcf871e5abd621613b12cd09beec61ac (MD5) Previous issue date: 1992","Item marked as restricted to the 'UIUC Users [automated]' Group (id=2) by Howard Ding (hding2@illinois.edu) on 2011-05-07T15:02:22Z Item is restricted indefinitely.","Restriction data tranferred 2014-07-01T11:29:39-05:00 Original Data Group with Access UIUC Users [automated] Release Date: none Reason: ETDs are only available to UIUC Users without author permission","ETDs are only available to UIUC Users without author permission","U of I Only"]},{"key":"dc:title","label":"Title","values":["Reducing memory access delays in large-scale shared-memory multiprocessors"]}]}],"canonical_facts":{"dc:contributor":["Veidenbaum, Alexander V."],"dc:creator":["Granston, Elana Denise"],"dc:date":["2011-05-07T14:03:10Z","10000-01-01","1992"],"dc:description":["Memory access time is a key factor limiting the performance of large-scale, shared-memory multiprocessors. In such systems, limited bandwidth in the interconnection between the processors and the memories, coupled with long delays resulting from network and memory conflicts, can produce serious memory access delays. Incorporating memory hierarchies and asynchronous block transfer mechanisms are common methods for reducing these delays. However, for these two mechanisms to be wed advantageously, they must be managed effectively, either in hardware or in software. Although this memory management problem is becoming increasingly important, good techniques are still lacking.","The problem of reducing memory access delays can be attacked at several levels. The first is to attempt to improve the performance of the shared-memory system itself, where the shared-memory system includes implicitly both the network and the memory modules themselves. The second is to develop techniques to manage the memory hierarchy more effectively and to make use of the block transfer mechanisms.","This thesis addresses this problem at both of these levels. The first part examines the behavior of a realistic shared-memory system and evaluates cost-effective hardware modifications for improving this balance. An additional goal is to achieve memory system scalability, where the term scalable describes systems whose per-processor performance is roughly constant across the range of system sizes examined.","The remainder of this thesis addresses the problem of improving utilization of local storage in shared-memory systems where, at the very least, each processor has access to local (private) storage in addition to the global (shared) memory. A combined flow-and-dependence analysis algorithm is developed which produces the analytical information needed to optimize data accesses. It is shown how this information can be used as part of an intergrated hardware/software approach to eliminating redundant (unnecessary) memory accesses and prefetching data.","Made available in DSpace on 2011-05-07T14:03:10Z (GMT). No. of bitstreams: 2 license.txt: 4922 bytes, checksum: 910b249b4beec47e7ab768910c8f966f (MD5) 9305540.pdf: 5060491 bytes, checksum: fcf871e5abd621613b12cd09beec61ac (MD5) Previous issue date: 1992","Item marked as restricted to the 'UIUC Users [automated]' Group (id=2) by Howard Ding (hding2@illinois.edu) on 2011-05-07T15:02:22Z Item is restricted indefinitely.","Restriction data tranferred 2014-07-01T11:29:39-05:00 Original Data Group with Access UIUC Users [automated] Release Date: none Reason: ETDs are only available to UIUC Users without author permission","ETDs are only available to UIUC Users without author permission","U of I Only"],"dc:identifier":["AAI9305540","(UMI)AAI9305540","http://hdl.handle.net/2142/23128"],"dc:language":["eng"],"dc:rights":["Copyright 1992 Granston, Elana Denise"],"dc:subject":["Computer Science"],"dc:title":["Reducing memory access delays in large-scale shared-memory multiprocessors"],"dc:type":["text"],"thesis:degree_discipline":["Computer Science"],"thesis:degree_level":["Dissertation"],"thesis:degree_name":["Ph.D."],"thesis:institution_name":["University of Illinois at Urbana-Champaign"]},"updated_at":"2026-07-22T22:25:21Z"}