{"id":{"repo_id":"uiuc","oai_identifier":"oai:www.ideals.illinois.edu:2142/23088"},"canonical_url":"https://search.dev.ndltd.org/etd/uiuc/oai:www.ideals.illinois.edu:2142/23088","repository":{"repo_id":"uiuc","name":"University of Illinois - Urbana-Champaign","base_url":"https://www.ideals.illinois.edu/oai-pmh"},"display":{"title":"Measurement-based performance analysis and modeling of parallel systems","abstract":"ETDs are only available to UIUC Users without author permission","abstract_html":"ETDs are only available to UIUC Users without author permission","abstract_has_math":false,"creators":["Natarajan, Chitra"],"institution":"University of Illinois at Urbana-Champaign","degree_name":"Ph.D.","degree_level":"Dissertation","degree_discipline":"Electrical Engineering","degree_department":null,"school":null,"contributors":["Iyer, Ravishankar K."],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2011,"date_issued":"2011-05-07T14:01:43Z","date_published":"2011-05-07T14:01:43Z","updated_at":"2026-07-22T22:25:21Z","subjects":["Engineering, Electronics and Electrical","Computer Science"],"languages":["eng"],"rights":["Copyright 1996 Natarajan, Chitra"],"rights_urls":[],"identifier_entries":[{"key":"dc:identifier","label":"Identifier","values":["AAI9712385","(UMI)AAI9712385","9780591198423"],"render_values":[{"text":"AAI9712385","href":null,"code":true},{"text":"(UMI)AAI9712385","href":null,"code":true},{"text":"9780591198423","href":null,"code":true}]}]},"links":{"outbound_url":"http://hdl.handle.net/2142/23088","outbound_label":"Handle","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Iyer, Ravishankar K."]},{"key":"dc:creator","label":"Author","values":["Natarajan, Chitra"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2011-05-07T14:01:43Z","10000-01-01","1996"]},{"key":"dc:type","label":"Dc Type","values":["text"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Electrical Engineering"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Dissertation"]},{"key":"thesis:degree_name","label":"Degree Name","values":["Ph.D."]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["University of Illinois at Urbana-Champaign"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Engineering, Electronics and Electrical","Computer Science"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language","label":"Dc Language","values":["eng"]},{"key":"dc:rights","label":"Dc Rights","values":["Copyright 1996 Natarajan, Chitra"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["AAI9712385","(UMI)AAI9712385","9780591198423","http://hdl.handle.net/2142/23088"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["ETDs are only available to UIUC Users without author permission","U of I Only","The CPUs, memory, interconnection network, operating system, runtime system, I/O subsystem, and application characteristics all play an important role in determining the overall performance obtained from a parallel system. However, previous studies have mostly looked at the memory or the OS or the network performance in isolation. A global view of the overheads from different system perspectives has been lacking. In this dissertation, we characterize the overheads for large application benchmarks executing on the Cedar shared-memory parallel system from operating system, runtime system parallelization, and global memory and interconnection network contention perspectives.","Parallel systems are often used in multiprogrammed environments. However, the issue of scalability in multiprogrammed shared-memory parallel systems has not been studied before. We investigate the scalability of the Cedar system in multiprogrammed environments and show that there is no performance improvement with scaling for fine-grained loop parallel applications executing in multiprogrammed workloads. We also demonstrate that there is an exponential drop in the overhead due to multiprogramming as the loop granularity is increased. We then propose and implement a self-preemption technique to improve the performance of fine-grained applications in multiprogrammed environments.","To balance the processor performance of parallel systems with sufficient I/O performance, several parallel I/O systems have been developed in recent years. However, very little is understood about their performance. We characterize the performance of the PIOUS parallel I/O system on the DEC Alphacluster, via real system measurements, and show that the message passing processing overheads at the compute and I/O nodes limit the throughput that they can sustain. We also use these measurements to provide realistic input parameters to PioSim, a parallel I/O simulation environment we have developed.","PioSim offers a number of unique features: (1) two architecture models--remote and local disk architecture models, (2) two usage models--simple and intelligent parallel I/O models, and (3) an application-oriented synthetic parallel I/O workload generator, PioSyn, capable of modeling a wide variety of temporal and spatial application file access patterns. We illustrate the potential of PioSim and PioSyn through experiments on the Alphacluster model, for scientific, database, and videoserver workloads.","Made available in DSpace on 2011-05-07T14:01:43Z (GMT). No. of bitstreams: 2 license.txt: 4922 bytes, checksum: 910b249b4beec47e7ab768910c8f966f (MD5) 9712385.pdf: 7566819 bytes, checksum: 547e7579cd25ac12cfa69b94de047d3c (MD5) Previous issue date: 1996","Item marked as restricted to the 'UIUC Users [automated]' Group (id=2) by Howard Ding (hding2@illinois.edu) on 2011-05-07T15:02:06Z Item is restricted indefinitely.","Restriction data tranferred 2014-07-01T11:29:30-05:00 Original Data Group with Access UIUC Users [automated] Release Date: none Reason: ETDs are only available to UIUC Users without author permission"]},{"key":"dc:title","label":"Title","values":["Measurement-based performance analysis and modeling of parallel systems"]}]}],"canonical_facts":{"dc:contributor":["Iyer, Ravishankar K."],"dc:creator":["Natarajan, Chitra"],"dc:date":["2011-05-07T14:01:43Z","10000-01-01","1996"],"dc:description":["ETDs are only available to UIUC Users without author permission","U of I Only","The CPUs, memory, interconnection network, operating system, runtime system, I/O subsystem, and application characteristics all play an important role in determining the overall performance obtained from a parallel system. However, previous studies have mostly looked at the memory or the OS or the network performance in isolation. A global view of the overheads from different system perspectives has been lacking. In this dissertation, we characterize the overheads for large application benchmarks executing on the Cedar shared-memory parallel system from operating system, runtime system parallelization, and global memory and interconnection network contention perspectives.","Parallel systems are often used in multiprogrammed environments. However, the issue of scalability in multiprogrammed shared-memory parallel systems has not been studied before. We investigate the scalability of the Cedar system in multiprogrammed environments and show that there is no performance improvement with scaling for fine-grained loop parallel applications executing in multiprogrammed workloads. We also demonstrate that there is an exponential drop in the overhead due to multiprogramming as the loop granularity is increased. We then propose and implement a self-preemption technique to improve the performance of fine-grained applications in multiprogrammed environments.","To balance the processor performance of parallel systems with sufficient I/O performance, several parallel I/O systems have been developed in recent years. However, very little is understood about their performance. We characterize the performance of the PIOUS parallel I/O system on the DEC Alphacluster, via real system measurements, and show that the message passing processing overheads at the compute and I/O nodes limit the throughput that they can sustain. We also use these measurements to provide realistic input parameters to PioSim, a parallel I/O simulation environment we have developed.","PioSim offers a number of unique features: (1) two architecture models--remote and local disk architecture models, (2) two usage models--simple and intelligent parallel I/O models, and (3) an application-oriented synthetic parallel I/O workload generator, PioSyn, capable of modeling a wide variety of temporal and spatial application file access patterns. We illustrate the potential of PioSim and PioSyn through experiments on the Alphacluster model, for scientific, database, and videoserver workloads.","Made available in DSpace on 2011-05-07T14:01:43Z (GMT). No. of bitstreams: 2 license.txt: 4922 bytes, checksum: 910b249b4beec47e7ab768910c8f966f (MD5) 9712385.pdf: 7566819 bytes, checksum: 547e7579cd25ac12cfa69b94de047d3c (MD5) Previous issue date: 1996","Item marked as restricted to the 'UIUC Users [automated]' Group (id=2) by Howard Ding (hding2@illinois.edu) on 2011-05-07T15:02:06Z Item is restricted indefinitely.","Restriction data tranferred 2014-07-01T11:29:30-05:00 Original Data Group with Access UIUC Users [automated] Release Date: none Reason: ETDs are only available to UIUC Users without author permission"],"dc:identifier":["AAI9712385","(UMI)AAI9712385","9780591198423","http://hdl.handle.net/2142/23088"],"dc:language":["eng"],"dc:rights":["Copyright 1996 Natarajan, Chitra"],"dc:subject":["Engineering, Electronics and Electrical","Computer Science"],"dc:title":["Measurement-based performance analysis and modeling of parallel systems"],"dc:type":["text"],"thesis:degree_discipline":["Electrical Engineering"],"thesis:degree_level":["Dissertation"],"thesis:degree_name":["Ph.D."],"thesis:institution_name":["University of Illinois at Urbana-Champaign"]},"updated_at":"2026-07-22T22:25:21Z"}