{"id":{"repo_id":"uiuc","oai_identifier":"oai:www.ideals.illinois.edu:2142/22968"},"canonical_url":"https://search.dev.ndltd.org/etd/uiuc/oai:www.ideals.illinois.edu:2142/22968","repository":{"repo_id":"uiuc","name":"University of Illinois - Urbana-Champaign","base_url":"https://www.ideals.illinois.edu/oai-pmh"},"display":{"title":"A design theory for totally self-checking and concurrent error detecting arithmetic circuits","abstract":"This thesis presents the results of an investigation into the applicability of Arithmetic Decomposition Theory (a theory for the design and analysis of arithmetic structures) to the design of concurrent error detecting arithmetic structures. Arithmetic Decomposition Theory shows how large, complex arithmetic circuits can be constructed by interconnecting a number of devices from a small library of elementary modules. The majority of effort in this investigation has gone into extending Arithmetic Decomposition Theory to encompass the design of Totally Self-Checking arithmetic circuits. Totally Self-Checking circuits always either produce a correct output, or give an error indication when a fault in the circuit causes an erroneous output. The extended theory has been demonstrated by its application to the design of a general purpose ALU. A simulator, which is useful in the analysis of Totally Self-Checking arithmetic circuits has been implemented. Finally, an alternative approach to concurrent error detection which involves a generalization of the classic approach of parity prediction to the two dimensional structures of Arithmetic Decomposition Theory has been developed.","abstract_html":"This thesis presents the results of an investigation into the applicability of Arithmetic Decomposition Theory (a theory for the design and analysis of arithmetic structures) to the design of concurrent error detecting arithmetic structures. Arithmetic Decomposition Theory shows how large, complex arithmetic circuits can be constructed by interconnecting a number of devices from a small library of elementary modules. The majority of effort in this investigation has gone into extending Arithmetic Decomposition Theory to encompass the design of Totally Self-Checking arithmetic circuits. Totally Self-Checking circuits always either produce a correct output, or give an error indication when a fault in the circuit causes an erroneous output. The extended theory has been demonstrated by its application to the design of a general purpose ALU. A simulator, which is useful in the analysis of Totally Self-Checking arithmetic circuits has been implemented. Finally, an alternative approach to concurrent error detection which involves a generalization of the classic approach of parity prediction to the two dimensional structures of Arithmetic Decomposition Theory has been developed.","abstract_has_math":false,"creators":["Angelotti, Frank William"],"institution":"University of Illinois at Urbana-Champaign","degree_name":"Ph.D.","degree_level":"Dissertation","degree_discipline":"Engineering, Electronics and Electrical","degree_department":null,"school":null,"contributors":["Robertson, James E."],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2011,"date_issued":"2011-05-07T13:57:32Z","date_published":"2011-05-07T13:57:32Z","updated_at":"2026-07-22T22:25:21Z","subjects":["Engineering, Electronics and Electrical","Computer Science"],"languages":["eng"],"rights":["Copyright 1990 Angelotti, Frank William"],"rights_urls":[],"identifier_entries":[{"key":"dc:identifier","label":"Identifier","values":["(UMI)AAI9026123","AAI9026123"],"render_values":[{"text":"(UMI)AAI9026123","href":null,"code":true},{"text":"AAI9026123","href":null,"code":true}]}]},"links":{"outbound_url":"http://hdl.handle.net/2142/22968","outbound_label":"Handle","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Robertson, James E."]},{"key":"dc:creator","label":"Author","values":["Angelotti, Frank William"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2011-05-07T13:57:32Z","10000-01-01","1990"]},{"key":"dc:type","label":"Dc Type","values":["text"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Engineering, Electronics and Electrical","Computer Science"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Dissertation"]},{"key":"thesis:degree_name","label":"Degree Name","values":["Ph.D."]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["University of Illinois at Urbana-Champaign"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Engineering, Electronics and Electrical","Computer Science"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language","label":"Dc Language","values":["eng"]},{"key":"dc:rights","label":"Dc Rights","values":["Copyright 1990 Angelotti, Frank William"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["(UMI)AAI9026123","AAI9026123","http://hdl.handle.net/2142/22968"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["This thesis presents the results of an investigation into the applicability of Arithmetic Decomposition Theory (a theory for the design and analysis of arithmetic structures) to the design of concurrent error detecting arithmetic structures. Arithmetic Decomposition Theory shows how large, complex arithmetic circuits can be constructed by interconnecting a number of devices from a small library of elementary modules. The majority of effort in this investigation has gone into extending Arithmetic Decomposition Theory to encompass the design of Totally Self-Checking arithmetic circuits. Totally Self-Checking circuits always either produce a correct output, or give an error indication when a fault in the circuit causes an erroneous output. The extended theory has been demonstrated by its application to the design of a general purpose ALU. A simulator, which is useful in the analysis of Totally Self-Checking arithmetic circuits has been implemented. Finally, an alternative approach to concurrent error detection which involves a generalization of the classic approach of parity prediction to the two dimensional structures of Arithmetic Decomposition Theory has been developed.","Made available in DSpace on 2011-05-07T13:57:32Z (GMT). No. of bitstreams: 2 license.txt: 4922 bytes, checksum: 910b249b4beec47e7ab768910c8f966f (MD5) 9026123.pdf: 3943319 bytes, checksum: 151e06bb8fe4ace3865f229fb4ba84d9 (MD5) Previous issue date: 1990","Item marked as restricted to the 'UIUC Users [automated]' Group (id=2) by Howard Ding (hding2@illinois.edu) on 2011-05-07T15:01:15Z Item is restricted indefinitely.","Restriction data tranferred 2014-07-01T11:29:03-05:00 Original Data Group with Access UIUC Users [automated] Release Date: none Reason: ETDs are only available to UIUC Users without author permission","ETDs are only available to UIUC Users without author permission","U of I Only"]},{"key":"dc:title","label":"Title","values":["A design theory for totally self-checking and concurrent error detecting arithmetic circuits"]}]}],"canonical_facts":{"dc:contributor":["Robertson, James E."],"dc:creator":["Angelotti, Frank William"],"dc:date":["2011-05-07T13:57:32Z","10000-01-01","1990"],"dc:description":["This thesis presents the results of an investigation into the applicability of Arithmetic Decomposition Theory (a theory for the design and analysis of arithmetic structures) to the design of concurrent error detecting arithmetic structures. Arithmetic Decomposition Theory shows how large, complex arithmetic circuits can be constructed by interconnecting a number of devices from a small library of elementary modules. The majority of effort in this investigation has gone into extending Arithmetic Decomposition Theory to encompass the design of Totally Self-Checking arithmetic circuits. Totally Self-Checking circuits always either produce a correct output, or give an error indication when a fault in the circuit causes an erroneous output. The extended theory has been demonstrated by its application to the design of a general purpose ALU. A simulator, which is useful in the analysis of Totally Self-Checking arithmetic circuits has been implemented. Finally, an alternative approach to concurrent error detection which involves a generalization of the classic approach of parity prediction to the two dimensional structures of Arithmetic Decomposition Theory has been developed.","Made available in DSpace on 2011-05-07T13:57:32Z (GMT). No. of bitstreams: 2 license.txt: 4922 bytes, checksum: 910b249b4beec47e7ab768910c8f966f (MD5) 9026123.pdf: 3943319 bytes, checksum: 151e06bb8fe4ace3865f229fb4ba84d9 (MD5) Previous issue date: 1990","Item marked as restricted to the 'UIUC Users [automated]' Group (id=2) by Howard Ding (hding2@illinois.edu) on 2011-05-07T15:01:15Z Item is restricted indefinitely.","Restriction data tranferred 2014-07-01T11:29:03-05:00 Original Data Group with Access UIUC Users [automated] Release Date: none Reason: ETDs are only available to UIUC Users without author permission","ETDs are only available to UIUC Users without author permission","U of I Only"],"dc:identifier":["(UMI)AAI9026123","AAI9026123","http://hdl.handle.net/2142/22968"],"dc:language":["eng"],"dc:rights":["Copyright 1990 Angelotti, Frank William"],"dc:subject":["Engineering, Electronics and Electrical","Computer Science"],"dc:title":["A design theory for totally self-checking and concurrent error detecting arithmetic circuits"],"dc:type":["text"],"thesis:degree_discipline":["Engineering, Electronics and Electrical","Computer Science"],"thesis:degree_level":["Dissertation"],"thesis:degree_name":["Ph.D."],"thesis:institution_name":["University of Illinois at Urbana-Champaign"]},"updated_at":"2026-07-22T22:25:21Z"}