{"id":{"repo_id":"uiuc","oai_identifier":"oai:www.ideals.illinois.edu:2142/22966"},"canonical_url":"https://search.dev.ndltd.org/etd/uiuc/oai:www.ideals.illinois.edu:2142/22966","repository":{"repo_id":"uiuc","name":"University of Illinois - Urbana-Champaign","base_url":"https://www.ideals.illinois.edu/oai-pmh"},"display":{"title":"Diagnosis and correction of logic design errors","abstract":"A CAD tool ACCORD has been developed for design verification and design error correction. ACCORD verifies a gate-level implementation of a design in terms of its functional description. If the functionality of an implementation is incorrect, the tool identifies the error locations and makes corrections automatically.","abstract_html":"A CAD tool ACCORD has been developed for design verification and design error correction. ACCORD verifies a gate-level implementation of a design in terms of its functional description. If the functionality of an implementation is incorrect, the tool identifies the error locations and makes corrections automatically.","abstract_has_math":false,"creators":["Chung, Pi-Yu"],"institution":"University of Illinois at Urbana-Champaign","degree_name":"Ph.D.","degree_level":"Dissertation","degree_discipline":"Engineering, Electronics and Electrical","degree_department":null,"school":null,"contributors":["Hajj, Ibrahim N."],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2011,"date_issued":"2011-05-07T13:57:29Z","date_published":"2011-05-07T13:57:29Z","updated_at":"2026-07-22T22:25:21Z","subjects":["Engineering, Electronics and Electrical","Computer Science"],"languages":["eng"],"rights":["Copyright 1994 Chung, Pi-Yu"],"rights_urls":[],"identifier_entries":[{"key":"dc:identifier","label":"Identifier","values":["AAI9416349","(UMI)AAI9416349"],"render_values":[{"text":"AAI9416349","href":null,"code":true},{"text":"(UMI)AAI9416349","href":null,"code":true}]}]},"links":{"outbound_url":"http://hdl.handle.net/2142/22966","outbound_label":"Handle","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Hajj, Ibrahim N."]},{"key":"dc:creator","label":"Author","values":["Chung, Pi-Yu"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2011-05-07T13:57:29Z","10000-01-01","1994"]},{"key":"dc:type","label":"Dc Type","values":["text"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Engineering, Electronics and Electrical","Computer Science"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Dissertation"]},{"key":"thesis:degree_name","label":"Degree Name","values":["Ph.D."]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["University of Illinois at Urbana-Champaign"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Engineering, Electronics and Electrical","Computer Science"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language","label":"Dc Language","values":["eng"]},{"key":"dc:rights","label":"Dc Rights","values":["Copyright 1994 Chung, Pi-Yu"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["AAI9416349","(UMI)AAI9416349","http://hdl.handle.net/2142/22966"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["A CAD tool ACCORD has been developed for design verification and design error correction. ACCORD verifies a gate-level implementation of a design in terms of its functional description. If the functionality of an implementation is incorrect, the tool identifies the error locations and makes corrections automatically.","Our approach is based on the simple design error model proposed by Abadir et al. (1). The model includes eight commonly encountered design errors: simple gate replacement, a missing/extra inverter, a missing/extra gate, a missing/extra gate input and an incorrectly placed gate input. The experiment described in (2) showed that the simple design error model covers 98% of the errors made by designers.","The main contributions of this thesis are (1) developing an efficient and exact search algorithm for single design error; (2) proposing fast gate correction and line correction procedures; and (3) extending the search and correction methods to rectify multiple design errors.","Experimental results on ISCAS and MCNC benchmark circuits show that 100% of single design errors, 68% of two design errors and 54% of three design errors can be corrected by our tool within an hour of CPU time.","Made available in DSpace on 2011-05-07T13:57:29Z (GMT). No. of bitstreams: 2 license.txt: 4922 bytes, checksum: 910b249b4beec47e7ab768910c8f966f (MD5) 9416349.pdf: 4021590 bytes, checksum: 496822eb556448103c75e5fca2c6b867 (MD5) Previous issue date: 1994","Item marked as restricted to the 'UIUC Users [automated]' Group (id=2) by Howard Ding (hding2@illinois.edu) on 2011-05-07T15:01:15Z Item is restricted indefinitely.","Restriction data tranferred 2014-07-01T11:29:03-05:00 Original Data Group with Access UIUC Users [automated] Release Date: none Reason: ETDs are only available to UIUC Users without author permission","ETDs are only available to UIUC Users without author permission","U of I Only"]},{"key":"dc:title","label":"Title","values":["Diagnosis and correction of logic design errors"]}]}],"canonical_facts":{"dc:contributor":["Hajj, Ibrahim N."],"dc:creator":["Chung, Pi-Yu"],"dc:date":["2011-05-07T13:57:29Z","10000-01-01","1994"],"dc:description":["A CAD tool ACCORD has been developed for design verification and design error correction. ACCORD verifies a gate-level implementation of a design in terms of its functional description. If the functionality of an implementation is incorrect, the tool identifies the error locations and makes corrections automatically.","Our approach is based on the simple design error model proposed by Abadir et al. (1). The model includes eight commonly encountered design errors: simple gate replacement, a missing/extra inverter, a missing/extra gate, a missing/extra gate input and an incorrectly placed gate input. The experiment described in (2) showed that the simple design error model covers 98% of the errors made by designers.","The main contributions of this thesis are (1) developing an efficient and exact search algorithm for single design error; (2) proposing fast gate correction and line correction procedures; and (3) extending the search and correction methods to rectify multiple design errors.","Experimental results on ISCAS and MCNC benchmark circuits show that 100% of single design errors, 68% of two design errors and 54% of three design errors can be corrected by our tool within an hour of CPU time.","Made available in DSpace on 2011-05-07T13:57:29Z (GMT). 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