{"id":{"repo_id":"uiuc","oai_identifier":"oai:www.ideals.illinois.edu:2142/22776"},"canonical_url":"https://search.dev.ndltd.org/etd/uiuc/oai:www.ideals.illinois.edu:2142/22776","repository":{"repo_id":"uiuc","name":"University of Illinois - Urbana-Champaign","base_url":"https://www.ideals.illinois.edu/oai-pmh"},"display":{"title":"Symbolic techniques for VLSI test and diagnosis","abstract":"Many problems in the domain of digital circuit testing and diagnosis demand the processing of a large number of circuit configurations. Recently, due to the development of binary decision diagrams (BDDs), symbolic methods have become a practical means of handling the large sets encountered in these applications. In this thesis, several algorithms are presented which make use of BDDs to address problems in digital circuit testing and diagnosis.","abstract_html":"Many problems in the domain of digital circuit testing and diagnosis demand the processing of a large number of circuit configurations. Recently, due to the development of binary decision diagrams (BDDs), symbolic methods have become a practical means of handling the large sets encountered in these applications. In this thesis, several algorithms are presented which make use of BDDs to address problems in digital circuit testing and diagnosis.","abstract_has_math":false,"creators":["Kubiak, Kenneth Edward"],"institution":"University of Illinois at Urbana-Champaign","degree_name":"Ph.D.","degree_level":"Dissertation","degree_discipline":"Electrical and Computer Engineering","degree_department":null,"school":null,"contributors":["Fuchs, W. Kent"],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2011,"date_issued":"2011-05-07T13:51:08Z","date_published":"2011-05-07T13:51:08Z","updated_at":"2026-07-22T22:25:20Z","subjects":["Engineering, Electronics and Electrical","Computer Science"],"languages":["eng"],"rights":["Copyright 1994 Kubiak, Kenneth Edward"],"rights_urls":[],"identifier_entries":[{"key":"dc:identifier","label":"Identifier","values":["(UMI)AAI9416388","AAI9416388"],"render_values":[{"text":"(UMI)AAI9416388","href":null,"code":true},{"text":"AAI9416388","href":null,"code":true}]}]},"links":{"outbound_url":"http://hdl.handle.net/2142/22776","outbound_label":"Handle","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Fuchs, W. Kent"]},{"key":"dc:creator","label":"Author","values":["Kubiak, Kenneth Edward"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2011-05-07T13:51:08Z","10000-01-01","1994"]},{"key":"dc:type","label":"Dc Type","values":["text"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Electrical and Computer Engineering"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Dissertation"]},{"key":"thesis:degree_name","label":"Degree Name","values":["Ph.D."]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["University of Illinois at Urbana-Champaign"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Engineering, Electronics and Electrical","Computer Science"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language","label":"Dc Language","values":["eng"]},{"key":"dc:rights","label":"Dc Rights","values":["Copyright 1994 Kubiak, Kenneth Edward"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["(UMI)AAI9416388","AAI9416388","http://hdl.handle.net/2142/22776"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["Many problems in the domain of digital circuit testing and diagnosis demand the processing of a large number of circuit configurations. Recently, due to the development of binary decision diagrams (BDDs), symbolic methods have become a practical means of handling the large sets encountered in these applications. In this thesis, several algorithms are presented which make use of BDDs to address problems in digital circuit testing and diagnosis.","Algorithms are presented for multiple-fault fault simulation, diagnostic fault simulation, test generation, and diagnostic test generation. The algorithms allow the circuit and fault model to be described generally in terms of Boolean functions, and are applicable to hierarchical or partitioned circuits. The procedures necessary to implement deterministic test generation algorithms are specified in terms of the Boolean differential calculus, and this theory provides a basis for test generation at levels of abstraction higher than the gate level. Several operations on BDDs are described which were developed during the course of this work and may be applicable to other domains.","Made available in DSpace on 2011-05-07T13:51:08Z (GMT). No. of bitstreams: 2 license.txt: 4922 bytes, checksum: 910b249b4beec47e7ab768910c8f966f (MD5) 9416388.pdf: 3700695 bytes, checksum: 91538df14de470cb660d32ce19112e12 (MD5) Previous issue date: 1994","Item marked as restricted to the 'UIUC Users [automated]' Group (id=2) by Howard Ding (hding2@illinois.edu) on 2011-05-07T14:59:55Z Item is restricted indefinitely.","Restriction data tranferred 2014-07-01T11:28:19-05:00 Original Data Group with Access UIUC Users [automated] Release Date: none Reason: ETDs are only available to UIUC Users without author permission","ETDs are only available to UIUC Users without author permission","U of I Only"]},{"key":"dc:title","label":"Title","values":["Symbolic techniques for VLSI test and diagnosis"]}]}],"canonical_facts":{"dc:contributor":["Fuchs, W. Kent"],"dc:creator":["Kubiak, Kenneth Edward"],"dc:date":["2011-05-07T13:51:08Z","10000-01-01","1994"],"dc:description":["Many problems in the domain of digital circuit testing and diagnosis demand the processing of a large number of circuit configurations. Recently, due to the development of binary decision diagrams (BDDs), symbolic methods have become a practical means of handling the large sets encountered in these applications. In this thesis, several algorithms are presented which make use of BDDs to address problems in digital circuit testing and diagnosis.","Algorithms are presented for multiple-fault fault simulation, diagnostic fault simulation, test generation, and diagnostic test generation. The algorithms allow the circuit and fault model to be described generally in terms of Boolean functions, and are applicable to hierarchical or partitioned circuits. The procedures necessary to implement deterministic test generation algorithms are specified in terms of the Boolean differential calculus, and this theory provides a basis for test generation at levels of abstraction higher than the gate level. Several operations on BDDs are described which were developed during the course of this work and may be applicable to other domains.","Made available in DSpace on 2011-05-07T13:51:08Z (GMT). No. of bitstreams: 2 license.txt: 4922 bytes, checksum: 910b249b4beec47e7ab768910c8f966f (MD5) 9416388.pdf: 3700695 bytes, checksum: 91538df14de470cb660d32ce19112e12 (MD5) Previous issue date: 1994","Item marked as restricted to the 'UIUC Users [automated]' Group (id=2) by Howard Ding (hding2@illinois.edu) on 2011-05-07T14:59:55Z Item is restricted indefinitely.","Restriction data tranferred 2014-07-01T11:28:19-05:00 Original Data Group with Access UIUC Users [automated] Release Date: none Reason: ETDs are only available to UIUC Users without author permission","ETDs are only available to UIUC Users without author permission","U of I Only"],"dc:identifier":["(UMI)AAI9416388","AAI9416388","http://hdl.handle.net/2142/22776"],"dc:language":["eng"],"dc:rights":["Copyright 1994 Kubiak, Kenneth Edward"],"dc:subject":["Engineering, Electronics and Electrical","Computer Science"],"dc:title":["Symbolic techniques for VLSI test and diagnosis"],"dc:type":["text"],"thesis:degree_discipline":["Electrical and Computer Engineering"],"thesis:degree_level":["Dissertation"],"thesis:degree_name":["Ph.D."],"thesis:institution_name":["University of Illinois at Urbana-Champaign"]},"updated_at":"2026-07-22T22:25:20Z"}