{"id":{"repo_id":"uiuc","oai_identifier":"oai:www.ideals.illinois.edu:2142/21293"},"canonical_url":"https://search.dev.ndltd.org/etd/uiuc/oai:www.ideals.illinois.edu:2142/21293","repository":{"repo_id":"uiuc","name":"University of Illinois - Urbana-Champaign","base_url":"https://www.ideals.illinois.edu/oai-pmh"},"display":{"title":"Full-band Monte Carlo simulation of hot electrons in scaled silicon devices","abstract":"\"A full-band Monte Carlo device simulator has been used to study the effects of device scaling on hot electrons in different types of n-channel MOSFETs and flash memory structures. A MOSFET with a single source/drain implant, an LDD MOSFET, an SOI MOSFET, and a MOSFET built on top of a heavily doped \"\"ground plane\"\" have been simulated. Different scaling techniques have been applied to the devices to see the effects on the electric field, the energy distributions of the electrons, and the drain, substrate, and gate currents. The locations of impact ionization events and injection into the gate oxide are examined. It is shown that simpler models cannot adequately predict hot carrier behavior at the channel lengths studied (below 0.3 $\\mu$m) and that several strategies that are successful at suppressing the hot carrier population for longer channel lengths are not as useful when 0.1 $\\mu$m channel lengths are approached. The effect of scaling on the programming of stacked-gate and split-gate flash memory devices was also studied. Predictions of hot carrier behavior in small MOSFETs and flash memory devices are made, and suggestions for device design are given.\"","abstract_html":"&quot;A full-band Monte Carlo device simulator has been used to study the effects of device scaling on hot electrons in different types of n-channel MOSFETs and flash memory structures. A MOSFET with a single source/drain implant, an LDD MOSFET, an SOI MOSFET, and a MOSFET built on top of a heavily doped &quot;&quot;ground plane&quot;&quot; have been simulated. Different scaling techniques have been applied to the devices to see the effects on the electric field, the energy distributions of the electrons, and the drain, substrate, and gate currents. The locations of impact ionization events and injection into the gate oxide are examined. It is shown that simpler models cannot adequately predict hot carrier behavior at the channel lengths studied (below 0.3 <span class=\"etd-inline-math\">&mu;</span>m) and that several strategies that are successful at suppressing the hot carrier population for longer channel lengths are not as useful when 0.1 <span class=\"etd-inline-math\">&mu;</span>m channel lengths are approached. The effect of scaling on the programming of stacked-gate and split-gate flash memory devices was also studied. Predictions of hot carrier behavior in small MOSFETs and flash memory devices are made, and suggestions for device design are given.&quot;","abstract_has_math":true,"creators":["Duncan, Amanda Watson"],"institution":"University of Illinois at Urbana-Champaign","degree_name":"Ph.D.","degree_level":"Dissertation","degree_discipline":"Electrical Engineering","degree_department":null,"school":null,"contributors":["Ravaioli, Umberto"],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2011,"date_issued":"2011-05-07T13:04:25Z","date_published":"2011-05-07T13:04:25Z","updated_at":"2026-07-22T22:25:17Z","subjects":["Engineering, Electronics and Electrical","Physics, Condensed Matter"],"languages":["eng"],"rights":["Copyright 1996 Duncan, Amanda Watson"],"rights_urls":[],"identifier_entries":[{"key":"dc:identifier","label":"Identifier","values":["9780591198034","AAI9712263","(UMI)AAI9712263"],"render_values":[{"text":"9780591198034","href":null,"code":true},{"text":"AAI9712263","href":null,"code":true},{"text":"(UMI)AAI9712263","href":null,"code":true}]}]},"links":{"outbound_url":"http://hdl.handle.net/2142/21293","outbound_label":"Handle","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Ravaioli, Umberto"]},{"key":"dc:creator","label":"Author","values":["Duncan, Amanda Watson"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2011-05-07T13:04:25Z","10000-01-01","1996"]},{"key":"dc:type","label":"Dc Type","values":["text"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Electrical Engineering"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Dissertation"]},{"key":"thesis:degree_name","label":"Degree Name","values":["Ph.D."]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["University of Illinois at Urbana-Champaign"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Engineering, Electronics and Electrical","Physics, Condensed Matter"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language","label":"Dc Language","values":["eng"]},{"key":"dc:rights","label":"Dc Rights","values":["Copyright 1996 Duncan, Amanda Watson"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["9780591198034","AAI9712263","(UMI)AAI9712263","http://hdl.handle.net/2142/21293"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["\"A full-band Monte Carlo device simulator has been used to study the effects of device scaling on hot electrons in different types of n-channel MOSFETs and flash memory structures. A MOSFET with a single source/drain implant, an LDD MOSFET, an SOI MOSFET, and a MOSFET built on top of a heavily doped \"\"ground plane\"\" have been simulated. Different scaling techniques have been applied to the devices to see the effects on the electric field, the energy distributions of the electrons, and the drain, substrate, and gate currents. The locations of impact ionization events and injection into the gate oxide are examined. It is shown that simpler models cannot adequately predict hot carrier behavior at the channel lengths studied (below 0.3 $\\mu$m) and that several strategies that are successful at suppressing the hot carrier population for longer channel lengths are not as useful when 0.1 $\\mu$m channel lengths are approached. The effect of scaling on the programming of stacked-gate and split-gate flash memory devices was also studied. Predictions of hot carrier behavior in small MOSFETs and flash memory devices are made, and suggestions for device design are given.\"","Made available in DSpace on 2011-05-07T13:04:25Z (GMT). No. of bitstreams: 2 license.txt: 4922 bytes, checksum: 910b249b4beec47e7ab768910c8f966f (MD5) 9712263.pdf: 3802884 bytes, checksum: b6f162c742898926848a58fb98a559da (MD5) Previous issue date: 1996","Item marked as restricted to the 'UIUC Users [automated]' Group (id=2) by Howard Ding (hding2@illinois.edu) on 2011-05-07T14:49:47Z Item is restricted indefinitely.","Restriction data tranferred 2014-07-01T11:22:41-05:00 Original Data Group with Access UIUC Users [automated] Release Date: none Reason: ETDs are only available to UIUC Users without author permission","ETDs are only available to UIUC Users without author permission","U of I Only"]},{"key":"dc:title","label":"Title","values":["Full-band Monte Carlo simulation of hot electrons in scaled silicon devices"]}]}],"canonical_facts":{"dc:contributor":["Ravaioli, Umberto"],"dc:creator":["Duncan, Amanda Watson"],"dc:date":["2011-05-07T13:04:25Z","10000-01-01","1996"],"dc:description":["\"A full-band Monte Carlo device simulator has been used to study the effects of device scaling on hot electrons in different types of n-channel MOSFETs and flash memory structures. A MOSFET with a single source/drain implant, an LDD MOSFET, an SOI MOSFET, and a MOSFET built on top of a heavily doped \"\"ground plane\"\" have been simulated. Different scaling techniques have been applied to the devices to see the effects on the electric field, the energy distributions of the electrons, and the drain, substrate, and gate currents. The locations of impact ionization events and injection into the gate oxide are examined. It is shown that simpler models cannot adequately predict hot carrier behavior at the channel lengths studied (below 0.3 $\\mu$m) and that several strategies that are successful at suppressing the hot carrier population for longer channel lengths are not as useful when 0.1 $\\mu$m channel lengths are approached. The effect of scaling on the programming of stacked-gate and split-gate flash memory devices was also studied. Predictions of hot carrier behavior in small MOSFETs and flash memory devices are made, and suggestions for device design are given.\"","Made available in DSpace on 2011-05-07T13:04:25Z (GMT). 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