{"id":{"repo_id":"uiuc","oai_identifier":"oai:www.ideals.illinois.edu:2142/21162"},"canonical_url":"https://search.dev.ndltd.org/etd/uiuc/oai:www.ideals.illinois.edu:2142/21162","repository":{"repo_id":"uiuc","name":"University of Illinois - Urbana-Champaign","base_url":"https://www.ideals.illinois.edu/oai-pmh"},"display":{"title":"Preparation and characterization of in situ deposited metal-insulator-III-V semiconductor devices","abstract":"In this thesis, the growth, fabrication, and characterization of in-situ deposited III-V semiconductor-based Metal-Insulator-Semiconductor (MIS) devices are described. The two III-V semiconductors investigated were $\\rm In\\sb{0.53}Ga\\sb{0.47}As$ and GaAs. The problems related to air exposure of the semiconductor surface in ex-situ process was circumvented in this work by depositing the insulator in-situ. A special growth system which integrates several MBE growth chambers with an ultrahigh vacuum chemical vapor deposition chamber was designed and built. All of the chambers in this growth system are connected by vacuum transfer tubes and sample transfer takes place under ultrahigh vacuum conditions. The technique of electron cyclotron resonance plasma-assisted deposition was used for the deposition of $\\rm Si\\sb3N\\sb4$ and Si.","abstract_html":"In this thesis, the growth, fabrication, and characterization of in-situ deposited III-V semiconductor-based Metal-Insulator-Semiconductor (MIS) devices are described. The two III-V semiconductors investigated were $\\rm In\\sb{0.53}Ga\\sb{0.47}As$ and GaAs. The problems related to air exposure of the semiconductor surface in ex-situ process was circumvented in this work by depositing the insulator in-situ. A special growth system which integrates several MBE growth chambers with an ultrahigh vacuum chemical vapor deposition chamber was designed and built. All of the chambers in this growth system are connected by vacuum transfer tubes and sample transfer takes place under ultrahigh vacuum conditions. The technique of electron cyclotron resonance plasma-assisted deposition was used for the deposition of $\\rm Si\\sb3N\\sb4$ and Si.","abstract_has_math":true,"creators":["Mui, David Sai Lai"],"institution":"University of Illinois at Urbana-Champaign","degree_name":"Ph.D.","degree_level":"Dissertation","degree_discipline":"Electrical Engineering","degree_department":null,"school":null,"contributors":["Morkoc, Hadis"],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2011,"date_issued":"2011-05-07T13:00:12Z","date_published":"2011-05-07T13:00:12Z","updated_at":"2026-07-22T22:25:17Z","subjects":["Engineering, Electronics and Electrical"],"languages":["eng"],"rights":["Copyright 1992 Mui, David Sai Lai"],"rights_urls":[],"identifier_entries":[{"key":"dc:identifier","label":"Identifier","values":["AAI9305627","(UMI)AAI9305627"],"render_values":[{"text":"AAI9305627","href":null,"code":true},{"text":"(UMI)AAI9305627","href":null,"code":true}]}]},"links":{"outbound_url":"http://hdl.handle.net/2142/21162","outbound_label":"Handle","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Morkoc, Hadis"]},{"key":"dc:creator","label":"Author","values":["Mui, David Sai Lai"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2011-05-07T13:00:12Z","10000-01-01","1992"]},{"key":"dc:type","label":"Dc Type","values":["text"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Electrical Engineering"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Dissertation"]},{"key":"thesis:degree_name","label":"Degree Name","values":["Ph.D."]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["University of Illinois at Urbana-Champaign"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Engineering, Electronics and Electrical"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language","label":"Dc Language","values":["eng"]},{"key":"dc:rights","label":"Dc Rights","values":["Copyright 1992 Mui, David Sai Lai"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["AAI9305627","(UMI)AAI9305627","http://hdl.handle.net/2142/21162"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["In this thesis, the growth, fabrication, and characterization of in-situ deposited III-V semiconductor-based Metal-Insulator-Semiconductor (MIS) devices are described. The two III-V semiconductors investigated were $\\rm In\\sb{0.53}Ga\\sb{0.47}As$ and GaAs. The problems related to air exposure of the semiconductor surface in ex-situ process was circumvented in this work by depositing the insulator in-situ. A special growth system which integrates several MBE growth chambers with an ultrahigh vacuum chemical vapor deposition chamber was designed and built. All of the chambers in this growth system are connected by vacuum transfer tubes and sample transfer takes place under ultrahigh vacuum conditions. The technique of electron cyclotron resonance plasma-assisted deposition was used for the deposition of $\\rm Si\\sb3N\\sb4$ and Si.","By using a spatially extended interface, the role of tunneling-related trapping in accumulation bias was discussed. It was shown that the circuit model on which the conventional SiO$\\sb2/$Si interface characterization techniques were based was not applicable when tunneling-related trapping occurred. A new circuit model appropriate for tunneling-related trapping was derived. Measured frequency dispersion on ICS interfaces was shown to be adequately explained by the new circuit model. With the new circuit model, the interface trap density near the conduction band edge and the effective thickness of the interface were deduced.","In order to utilize these start-of-the-art interfaces in MISFETs, a self-aligned gate process was developed. The gaps between the gate/drain and gate/source metallizations obtained from this self-aligned technique were of the order of 1000-2000 A. Extrinsic transconductances of close to 240 mS/mm of 2.2 $\\mu$m gate $\\rm In\\sb{0.53}Ga\\sb{0.47}As$ depletion mode MIS Field-Effect Transistors were obtained.","Made available in DSpace on 2011-05-07T13:00:12Z (GMT). No. of bitstreams: 2 license.txt: 4922 bytes, checksum: 910b249b4beec47e7ab768910c8f966f (MD5) 9305627.pdf: 5996552 bytes, checksum: 800c17ce72f24cfc8e665c3e2644a323 (MD5) Previous issue date: 1992","Item marked as restricted to the 'UIUC Users [automated]' Group (id=2) by Howard Ding (hding2@illinois.edu) on 2011-05-07T14:48:54Z Item is restricted indefinitely.","Restriction data tranferred 2014-07-01T11:22:11-05:00 Original Data Group with Access UIUC Users [automated] Release Date: none Reason: ETDs are only available to UIUC Users without author permission","ETDs are only available to UIUC Users without author permission","U of I Only"]},{"key":"dc:title","label":"Title","values":["Preparation and characterization of in situ deposited metal-insulator-III-V semiconductor devices"]}]}],"canonical_facts":{"dc:contributor":["Morkoc, Hadis"],"dc:creator":["Mui, David Sai Lai"],"dc:date":["2011-05-07T13:00:12Z","10000-01-01","1992"],"dc:description":["In this thesis, the growth, fabrication, and characterization of in-situ deposited III-V semiconductor-based Metal-Insulator-Semiconductor (MIS) devices are described. The two III-V semiconductors investigated were $\\rm In\\sb{0.53}Ga\\sb{0.47}As$ and GaAs. The problems related to air exposure of the semiconductor surface in ex-situ process was circumvented in this work by depositing the insulator in-situ. A special growth system which integrates several MBE growth chambers with an ultrahigh vacuum chemical vapor deposition chamber was designed and built. All of the chambers in this growth system are connected by vacuum transfer tubes and sample transfer takes place under ultrahigh vacuum conditions. The technique of electron cyclotron resonance plasma-assisted deposition was used for the deposition of $\\rm Si\\sb3N\\sb4$ and Si.","By using a spatially extended interface, the role of tunneling-related trapping in accumulation bias was discussed. It was shown that the circuit model on which the conventional SiO$\\sb2/$Si interface characterization techniques were based was not applicable when tunneling-related trapping occurred. A new circuit model appropriate for tunneling-related trapping was derived. Measured frequency dispersion on ICS interfaces was shown to be adequately explained by the new circuit model. With the new circuit model, the interface trap density near the conduction band edge and the effective thickness of the interface were deduced.","In order to utilize these start-of-the-art interfaces in MISFETs, a self-aligned gate process was developed. The gaps between the gate/drain and gate/source metallizations obtained from this self-aligned technique were of the order of 1000-2000 A. Extrinsic transconductances of close to 240 mS/mm of 2.2 $\\mu$m gate $\\rm In\\sb{0.53}Ga\\sb{0.47}As$ depletion mode MIS Field-Effect Transistors were obtained.","Made available in DSpace on 2011-05-07T13:00:12Z (GMT). No. of bitstreams: 2 license.txt: 4922 bytes, checksum: 910b249b4beec47e7ab768910c8f966f (MD5) 9305627.pdf: 5996552 bytes, checksum: 800c17ce72f24cfc8e665c3e2644a323 (MD5) Previous issue date: 1992","Item marked as restricted to the 'UIUC Users [automated]' Group (id=2) by Howard Ding (hding2@illinois.edu) on 2011-05-07T14:48:54Z Item is restricted indefinitely.","Restriction data tranferred 2014-07-01T11:22:11-05:00 Original Data Group with Access UIUC Users [automated] Release Date: none Reason: ETDs are only available to UIUC Users without author permission","ETDs are only available to UIUC Users without author permission","U of I Only"],"dc:identifier":["AAI9305627","(UMI)AAI9305627","http://hdl.handle.net/2142/21162"],"dc:language":["eng"],"dc:rights":["Copyright 1992 Mui, David Sai Lai"],"dc:subject":["Engineering, Electronics and Electrical"],"dc:title":["Preparation and characterization of in situ deposited metal-insulator-III-V semiconductor devices"],"dc:type":["text"],"thesis:degree_discipline":["Electrical Engineering"],"thesis:degree_level":["Dissertation"],"thesis:degree_name":["Ph.D."],"thesis:institution_name":["University of Illinois at Urbana-Champaign"]},"updated_at":"2026-07-22T22:25:17Z"}