{"id":{"repo_id":"uiuc","oai_identifier":"oai:www.ideals.illinois.edu:2142/18971"},"canonical_url":"https://search.dev.ndltd.org/etd/uiuc/oai:www.ideals.illinois.edu:2142/18971","repository":{"repo_id":"uiuc","name":"University of Illinois - Urbana-Champaign","base_url":"https://www.ideals.illinois.edu/oai-pmh"},"display":{"title":"PARASPICE: A parallel direct circuit simulator for shared-memory multiprocessors","abstract":"A general approach to parallelizing direct method circuit simulation has been developed via novel algorithms. The approach extracts parallel tasks at the algorithmic level for the three most compute-intensive modules: device model evaluation (LOAD), direct solution of sparse linear systems (SOLVE), and local truncation error estimation (TRUNC), which account for at least 95 percent of the total job time. Therefore, it is suitable for a wide range of shared-memory multiprocessors. The implementation of the approach in SPICE2 resulted in a portable parallel direct circuit simulator, PARASPICE. The superior performance of PARASPICE is demonstrated on an eight-CE Alliant FX/80 using a number of benchmark circuits.","abstract_html":"A general approach to parallelizing direct method circuit simulation has been developed via novel algorithms. The approach extracts parallel tasks at the algorithmic level for the three most compute-intensive modules: device model evaluation (LOAD), direct solution of sparse linear systems (SOLVE), and local truncation error estimation (TRUNC), which account for at least 95 percent of the total job time. Therefore, it is suitable for a wide range of shared-memory multiprocessors. The implementation of the approach in SPICE2 resulted in a portable parallel direct circuit simulator, PARASPICE. The superior performance of PARASPICE is demonstrated on an eight-CE Alliant FX/80 using a number of benchmark circuits.","abstract_has_math":false,"creators":["Yang, Gung-Chung"],"institution":"University of Illinois at Urbana-Champaign","degree_name":"Ph.D.","degree_level":"Dissertation","degree_discipline":"Computer Science","degree_department":null,"school":null,"contributors":["Sameh, Ahmed H."],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2011,"date_issued":"2011-05-07T11:53:02Z","date_published":"2011-05-07T11:53:02Z","updated_at":"2026-07-22T22:25:12Z","subjects":["Engineering, Electronics and Electrical","Computer Science"],"languages":["eng"],"rights":["Copyright 1990 Yang, Gung-Chung"],"rights_urls":[],"identifier_entries":[{"key":"dc:identifier","label":"Identifier","values":["AAI9026359","(UMI)AAI9026359"],"render_values":[{"text":"AAI9026359","href":null,"code":true},{"text":"(UMI)AAI9026359","href":null,"code":true}]}]},"links":{"outbound_url":"http://hdl.handle.net/2142/18971","outbound_label":"Handle","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Sameh, Ahmed H."]},{"key":"dc:creator","label":"Author","values":["Yang, Gung-Chung"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2011-05-07T11:53:02Z","10000-01-01","1990"]},{"key":"dc:type","label":"Dc Type","values":["text"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Computer Science"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Dissertation"]},{"key":"thesis:degree_name","label":"Degree Name","values":["Ph.D."]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["University of Illinois at Urbana-Champaign"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Engineering, Electronics and Electrical","Computer Science"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language","label":"Dc Language","values":["eng"]},{"key":"dc:rights","label":"Dc Rights","values":["Copyright 1990 Yang, Gung-Chung"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["AAI9026359","(UMI)AAI9026359","http://hdl.handle.net/2142/18971"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["A general approach to parallelizing direct method circuit simulation has been developed via novel algorithms. The approach extracts parallel tasks at the algorithmic level for the three most compute-intensive modules: device model evaluation (LOAD), direct solution of sparse linear systems (SOLVE), and local truncation error estimation (TRUNC), which account for at least 95 percent of the total job time. Therefore, it is suitable for a wide range of shared-memory multiprocessors. The implementation of the approach in SPICE2 resulted in a portable parallel direct circuit simulator, PARASPICE. The superior performance of PARASPICE is demonstrated on an eight-CE Alliant FX/80 using a number of benchmark circuits.","The success of PARASPICE lies particularly in the SOLVE module, where the solution of a sequence of structurally identical sparse matrices are required. In this dissertation, a class of new algorithms has been systematically developed via a unified model for parallel sparse matrix computation. This model, which explores the parallelism issue in the pivoting schemes, extracts parallel tasks from the solution procedure by exploiting the sparse structure of the matrix. These algorithms have been implemented in DSPACK, a software package for the direct solution of general sparse matrices. Experiments with DSPACK on the Boeing-Harwell collection of benchmark matrices have shown high overall speedup. DSPACK has been successfully used as a workbench to design parallel sparse solvers for circuit simulation.","Made available in DSpace on 2011-05-07T11:53:02Z (GMT). No. of bitstreams: 2 license.txt: 4922 bytes, checksum: 910b249b4beec47e7ab768910c8f966f (MD5) 9026359.pdf: 6667995 bytes, checksum: 08fa58b3ec72f76b16b65cfc32962d3e (MD5) Previous issue date: 1990","Item marked as restricted to the 'UIUC Users [automated]' Group (id=2) by Howard Ding (hding2@illinois.edu) on 2011-05-07T14:33:47Z Item is restricted indefinitely.","Restriction data tranferred 2014-07-01T11:12:37-05:00 Original Data Group with Access UIUC Users [automated] Release Date: none Reason: ETDs are only available to UIUC Users without author permission","ETDs are only available to UIUC Users without author permission","U of I Only"]},{"key":"dc:title","label":"Title","values":["PARASPICE: A parallel direct circuit simulator for shared-memory multiprocessors"]}]}],"canonical_facts":{"dc:contributor":["Sameh, Ahmed H."],"dc:creator":["Yang, Gung-Chung"],"dc:date":["2011-05-07T11:53:02Z","10000-01-01","1990"],"dc:description":["A general approach to parallelizing direct method circuit simulation has been developed via novel algorithms. The approach extracts parallel tasks at the algorithmic level for the three most compute-intensive modules: device model evaluation (LOAD), direct solution of sparse linear systems (SOLVE), and local truncation error estimation (TRUNC), which account for at least 95 percent of the total job time. Therefore, it is suitable for a wide range of shared-memory multiprocessors. The implementation of the approach in SPICE2 resulted in a portable parallel direct circuit simulator, PARASPICE. The superior performance of PARASPICE is demonstrated on an eight-CE Alliant FX/80 using a number of benchmark circuits.","The success of PARASPICE lies particularly in the SOLVE module, where the solution of a sequence of structurally identical sparse matrices are required. In this dissertation, a class of new algorithms has been systematically developed via a unified model for parallel sparse matrix computation. This model, which explores the parallelism issue in the pivoting schemes, extracts parallel tasks from the solution procedure by exploiting the sparse structure of the matrix. These algorithms have been implemented in DSPACK, a software package for the direct solution of general sparse matrices. Experiments with DSPACK on the Boeing-Harwell collection of benchmark matrices have shown high overall speedup. DSPACK has been successfully used as a workbench to design parallel sparse solvers for circuit simulation.","Made available in DSpace on 2011-05-07T11:53:02Z (GMT). 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