{"id":{"repo_id":"uiuc","oai_identifier":"oai:www.ideals.illinois.edu:2142/18955"},"canonical_url":"https://search.dev.ndltd.org/etd/uiuc/oai:www.ideals.illinois.edu:2142/18955","repository":{"repo_id":"uiuc","name":"University of Illinois - Urbana-Champaign","base_url":"https://www.ideals.illinois.edu/oai-pmh"},"display":{"title":"Performance-driven placement and routing algorithms","abstract":"As technology advances, the effect of intra-module delays become less significant, while the effect of inter-module interconnection delays become more prominent. Also, as power dissipation becomes an important issue in VLSI design, it is desirable for the signals to arrive at the inputs of the modules at the same time in order to reduce the number of unwanted transient switches. To minimize the signal arrival times of the primary output pins and the signal skews at the inputs of the modules, we developed a net-based performance driven placement algorithm and a path-based performance driven placement algorithm. As chip architectures become more specific (e.g., FPGA), it is important to consider the physical design information during logic design steps. Therefore, we developed a placement driven technology mapping algorithm for FPGA circuits. Finally, as technology advances, interconnection wires are placed in closer proximity and circuits operate at higher frequencies. Consequently, reduction in crosstalks between interconnection wires becomes an important consideration in VLSI design. To satisfy the crosstalk constraints and to minimize the total crosstalk among all the nets in a design, we developed a track permutation algorithm for gridded channel routing problems. We also developed a wire segment assignment algorithm for both channel routing problems and switchbox routing problems. The experimental results indicate that our algorithms are very promising.","abstract_html":"As technology advances, the effect of intra-module delays become less significant, while the effect of inter-module interconnection delays become more prominent. Also, as power dissipation becomes an important issue in VLSI design, it is desirable for the signals to arrive at the inputs of the modules at the same time in order to reduce the number of unwanted transient switches. To minimize the signal arrival times of the primary output pins and the signal skews at the inputs of the modules, we developed a net-based performance driven placement algorithm and a path-based performance driven placement algorithm. As chip architectures become more specific (e.g., FPGA), it is important to consider the physical design information during logic design steps. Therefore, we developed a placement driven technology mapping algorithm for FPGA circuits. Finally, as technology advances, interconnection wires are placed in closer proximity and circuits operate at higher frequencies. Consequently, reduction in crosstalks between interconnection wires becomes an important consideration in VLSI design. To satisfy the crosstalk constraints and to minimize the total crosstalk among all the nets in a design, we developed a track permutation algorithm for gridded channel routing problems. We also developed a wire segment assignment algorithm for both channel routing problems and switchbox routing problems. The experimental results indicate that our algorithms are very promising.","abstract_has_math":false,"creators":["Gao, Tong"],"institution":"University of Illinois at Urbana-Champaign","degree_name":"Ph.D.","degree_level":"Dissertation","degree_discipline":"Computer Science","degree_department":null,"school":null,"contributors":["Liu, C.L."],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2011,"date_issued":"2011-05-07T11:52:33Z","date_published":"2011-05-07T11:52:33Z","updated_at":"2026-07-22T22:25:12Z","subjects":["Computer Science"],"languages":["eng"],"rights":["Copyright 1994 Gao, Tong"],"rights_urls":[],"identifier_entries":[{"key":"dc:identifier","label":"Identifier","values":["AAI9512368","(UMI)AAI9512368"],"render_values":[{"text":"AAI9512368","href":null,"code":true},{"text":"(UMI)AAI9512368","href":null,"code":true}]}]},"links":{"outbound_url":"http://hdl.handle.net/2142/18955","outbound_label":"Handle","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Liu, C.L."]},{"key":"dc:creator","label":"Author","values":["Gao, Tong"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2011-05-07T11:52:33Z","10000-01-01","1994"]},{"key":"dc:type","label":"Dc Type","values":["text"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Computer Science"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Dissertation"]},{"key":"thesis:degree_name","label":"Degree Name","values":["Ph.D."]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["University of Illinois at Urbana-Champaign"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Computer Science"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language","label":"Dc Language","values":["eng"]},{"key":"dc:rights","label":"Dc Rights","values":["Copyright 1994 Gao, Tong"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["AAI9512368","(UMI)AAI9512368","http://hdl.handle.net/2142/18955"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["As technology advances, the effect of intra-module delays become less significant, while the effect of inter-module interconnection delays become more prominent. Also, as power dissipation becomes an important issue in VLSI design, it is desirable for the signals to arrive at the inputs of the modules at the same time in order to reduce the number of unwanted transient switches. To minimize the signal arrival times of the primary output pins and the signal skews at the inputs of the modules, we developed a net-based performance driven placement algorithm and a path-based performance driven placement algorithm. As chip architectures become more specific (e.g., FPGA), it is important to consider the physical design information during logic design steps. Therefore, we developed a placement driven technology mapping algorithm for FPGA circuits. Finally, as technology advances, interconnection wires are placed in closer proximity and circuits operate at higher frequencies. Consequently, reduction in crosstalks between interconnection wires becomes an important consideration in VLSI design. To satisfy the crosstalk constraints and to minimize the total crosstalk among all the nets in a design, we developed a track permutation algorithm for gridded channel routing problems. We also developed a wire segment assignment algorithm for both channel routing problems and switchbox routing problems. The experimental results indicate that our algorithms are very promising.","Made available in DSpace on 2011-05-07T11:52:33Z (GMT). No. of bitstreams: 2 license.txt: 4922 bytes, checksum: 910b249b4beec47e7ab768910c8f966f (MD5) 9512368.pdf: 4936032 bytes, checksum: fc3a0d53f6fb3340e26bd486ca70c0d9 (MD5) Previous issue date: 1994","Item marked as restricted to the 'UIUC Users [automated]' Group (id=2) by Howard Ding (hding2@illinois.edu) on 2011-05-07T14:33:40Z Item is restricted indefinitely.","Restriction data tranferred 2014-07-01T11:12:31-05:00 Original Data Group with Access UIUC Users [automated] Release Date: none Reason: ETDs are only available to UIUC Users without author permission","ETDs are only available to UIUC Users without author permission","U of I Only"]},{"key":"dc:title","label":"Title","values":["Performance-driven placement and routing algorithms"]}]}],"canonical_facts":{"dc:contributor":["Liu, C.L."],"dc:creator":["Gao, Tong"],"dc:date":["2011-05-07T11:52:33Z","10000-01-01","1994"],"dc:description":["As technology advances, the effect of intra-module delays become less significant, while the effect of inter-module interconnection delays become more prominent. Also, as power dissipation becomes an important issue in VLSI design, it is desirable for the signals to arrive at the inputs of the modules at the same time in order to reduce the number of unwanted transient switches. To minimize the signal arrival times of the primary output pins and the signal skews at the inputs of the modules, we developed a net-based performance driven placement algorithm and a path-based performance driven placement algorithm. As chip architectures become more specific (e.g., FPGA), it is important to consider the physical design information during logic design steps. Therefore, we developed a placement driven technology mapping algorithm for FPGA circuits. Finally, as technology advances, interconnection wires are placed in closer proximity and circuits operate at higher frequencies. Consequently, reduction in crosstalks between interconnection wires becomes an important consideration in VLSI design. To satisfy the crosstalk constraints and to minimize the total crosstalk among all the nets in a design, we developed a track permutation algorithm for gridded channel routing problems. We also developed a wire segment assignment algorithm for both channel routing problems and switchbox routing problems. The experimental results indicate that our algorithms are very promising.","Made available in DSpace on 2011-05-07T11:52:33Z (GMT). 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