{"id":{"repo_id":"uiuc","oai_identifier":"oai:www.ideals.illinois.edu:2142/18623"},"canonical_url":"https://search.dev.ndltd.org/etd/uiuc/oai:www.ideals.illinois.edu:2142/18623","repository":{"repo_id":"uiuc","name":"University of Illinois - Urbana-Champaign","base_url":"https://www.ideals.illinois.edu/oai-pmh"},"display":{"title":"Low-power high-performance SAR ADC design with digital calibration techniques","abstract":"This dissertation presents the design of three high-performance successive-approximation-register (SAR) analog-to-digital converters (ADCs) using distinct digital background calibration techniques under the framework of a generalized code-domain linear equalizer. These digital calibration techniques effectively and efficiently remove the static mismatch errors in the analog-to-digital (A/D) conversion. They enable aggressive scaling of the capacitive digital-to-analog converter (DAC), which also serves as sampling capacitor, to the kT/C limit. As a result, outstanding conversion linearity, high signal-to-noise ratio (SNR), high conversion speed, robustness, superb energy efficiency, and minimal chip-area are accomplished simultaneously. The first design is a 12-bit 22.5/45-MS/s SAR ADC in 0.13-μm CMOS process. It employs a perturbation-based calibration based on the superposition property of linear systems to digitally correct the capacitor mismatch error in the weighted DAC. With 3.0-mW power dissipation at a 1.2-V power supply and a 22.5-MS/s sample rate, it achieves a 71.1-dB signal-to-noise-plus-distortion ratio (SNDR), and a 94.6-dB spurious free dynamic range (SFDR). At Nyquist frequency, the conversion figure of merit (FoM) is 50.8 fJ/conversion step, the best FoM up to date (2010) for 12-bit ADCs. The SAR ADC core occupies 0.06 mm2, while the estimated area the calibration circuits is 0.03 mm2. The second proposed digital calibration technique is a bit-wise-correlation-based digital calibration. It utilizes the statistical independence of an injected pseudo-random signal and the input signal to correct the DAC mismatch in SAR ADCs. This idea is experimentally verified in a 12-bit 37-MS/s SAR ADC fabricated in 65-nm CMOS implemented by Pingli Huang. This prototype chip achieves a 70.23-dB peak SNDR and an 81.02-dB peak SFDR, while occupying 0.12-mm2 silicon area and dissipating 9.14 mW from a 1.2-V supply with the synthesized digital calibration circuits included. The third work is an 8-bit, 600-MS/s, 10-way time-interleaved SAR ADC array fabricated in 0.13-μm CMOS process. This work employs an adaptive digital equalization approach to calibrate both intra-channel nonlinearities and inter-channel mismatch errors. The prototype chip achieves 47.4-dB SNDR, 63.6-dB SFDR, less than 0.30-LSB differential nonlinearity (DNL), and less than 0.23-LSB integral nonlinearity (INL). The ADC array occupies an active area of 1.35 mm2 and dissipates 30.3 mW, including synthesized digital calibration circuits and an on-chip dual-loop delay-locked loop (DLL) for clock generation and synchronization.","abstract_html":"This dissertation presents the design of three high-performance successive-approximation-register (SAR) analog-to-digital converters (ADCs) using distinct digital background calibration techniques under the framework of a generalized code-domain linear equalizer. These digital calibration techniques effectively and efficiently remove the static mismatch errors in the analog-to-digital (A/D) conversion. They enable aggressive scaling of the capacitive digital-to-analog converter (DAC), which also serves as sampling capacitor, to the kT/C limit. As a result, outstanding conversion linearity, high signal-to-noise ratio (SNR), high conversion speed, robustness, superb energy efficiency, and minimal chip-area are accomplished simultaneously. The first design is a 12-bit 22.5/45-MS/s SAR ADC in 0.13-μm CMOS process. It employs a perturbation-based calibration based on the superposition property of linear systems to digitally correct the capacitor mismatch error in the weighted DAC. With 3.0-mW power dissipation at a 1.2-V power supply and a 22.5-MS/s sample rate, it achieves a 71.1-dB signal-to-noise-plus-distortion ratio (SNDR), and a 94.6-dB spurious free dynamic range (SFDR). At Nyquist frequency, the conversion figure of merit (FoM) is 50.8 fJ/conversion step, the best FoM up to date (2010) for 12-bit ADCs. The SAR ADC core occupies 0.06 mm2, while the estimated area the calibration circuits is 0.03 mm2. The second proposed digital calibration technique is a bit-wise-correlation-based digital calibration. It utilizes the statistical independence of an injected pseudo-random signal and the input signal to correct the DAC mismatch in SAR ADCs. This idea is experimentally verified in a 12-bit 37-MS/s SAR ADC fabricated in 65-nm CMOS implemented by Pingli Huang. This prototype chip achieves a 70.23-dB peak SNDR and an 81.02-dB peak SFDR, while occupying 0.12-mm2 silicon area and dissipating 9.14 mW from a 1.2-V supply with the synthesized digital calibration circuits included. The third work is an 8-bit, 600-MS/s, 10-way time-interleaved SAR ADC array fabricated in 0.13-μm CMOS process. This work employs an adaptive digital equalization approach to calibrate both intra-channel nonlinearities and inter-channel mismatch errors. The prototype chip achieves 47.4-dB SNDR, 63.6-dB SFDR, less than 0.30-LSB differential nonlinearity (DNL), and less than 0.23-LSB integral nonlinearity (INL). The ADC array occupies an active area of 1.35 mm2 and dissipates 30.3 mW, including synthesized digital calibration circuits and an on-chip dual-loop delay-locked loop (DLL) for clock generation and synchronization.","abstract_has_math":false,"creators":["Liu, Wenbo"],"institution":"University of Illinois at Urbana-Champaign","degree_name":"Ph.D.","degree_level":"Dissertation","degree_discipline":"Electrical & Computer Engr","degree_department":null,"school":null,"contributors":["Chiu, Yun","Shanbhag, Naresh R.","Rosenbaum, Elyse","Singer, Andrew C."],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2011,"date_issued":"2011-01-21T22:52:11Z","date_published":"2011-01-21T22:52:11Z","updated_at":"2026-07-22T22:25:11Z","subjects":["successive-approximation-register (SAR) analog-to-digital converters (ADC)","redundancy","sub-radix-2","Nonlinearity","digital calibration","linear equalizer","generalized linear equalizer","perturbation","bit-wise correlation","channel mismatch","time-interleaved analog-to-digital converters (ADC)"],"languages":["en"],"rights":["Copyright 2010 Wenbo Liu"],"rights_urls":[],"identifier_entries":[]},"links":{"outbound_url":"http://hdl.handle.net/2142/18623","outbound_label":"Handle","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Chiu, Yun","Shanbhag, Naresh R.","Rosenbaum, Elyse","Singer, Andrew C."]},{"key":"dc:creator","label":"Author","values":["Liu, Wenbo"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2011-01-21T22:52:11Z","2013-01-22T11:00:16Z","2010-12"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Electrical & Computer Engr"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Dissertation"]},{"key":"thesis:degree_name","label":"Degree Name","values":["Ph.D."]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["University of Illinois at Urbana-Champaign"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["successive-approximation-register (SAR) analog-to-digital converters (ADC)","redundancy","sub-radix-2","Nonlinearity","digital calibration","linear equalizer","generalized linear equalizer","perturbation","bit-wise correlation","channel mismatch","time-interleaved analog-to-digital converters (ADC)"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language","label":"Dc Language","values":["en"]},{"key":"dc:rights","label":"Dc Rights","values":["Copyright 2010 Wenbo Liu"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["http://hdl.handle.net/2142/18623"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["This dissertation presents the design of three high-performance successive-approximation-register (SAR) analog-to-digital converters (ADCs) using distinct digital background calibration techniques under the framework of a generalized code-domain linear equalizer. These digital calibration techniques effectively and efficiently remove the static mismatch errors in the analog-to-digital (A/D) conversion. They enable aggressive scaling of the capacitive digital-to-analog converter (DAC), which also serves as sampling capacitor, to the kT/C limit. As a result, outstanding conversion linearity, high signal-to-noise ratio (SNR), high conversion speed, robustness, superb energy efficiency, and minimal chip-area are accomplished simultaneously. The first design is a 12-bit 22.5/45-MS/s SAR ADC in 0.13-μm CMOS process. It employs a perturbation-based calibration based on the superposition property of linear systems to digitally correct the capacitor mismatch error in the weighted DAC. With 3.0-mW power dissipation at a 1.2-V power supply and a 22.5-MS/s sample rate, it achieves a 71.1-dB signal-to-noise-plus-distortion ratio (SNDR), and a 94.6-dB spurious free dynamic range (SFDR). At Nyquist frequency, the conversion figure of merit (FoM) is 50.8 fJ/conversion step, the best FoM up to date (2010) for 12-bit ADCs. The SAR ADC core occupies 0.06 mm2, while the estimated area the calibration circuits is 0.03 mm2. The second proposed digital calibration technique is a bit-wise-correlation-based digital calibration. It utilizes the statistical independence of an injected pseudo-random signal and the input signal to correct the DAC mismatch in SAR ADCs. This idea is experimentally verified in a 12-bit 37-MS/s SAR ADC fabricated in 65-nm CMOS implemented by Pingli Huang. This prototype chip achieves a 70.23-dB peak SNDR and an 81.02-dB peak SFDR, while occupying 0.12-mm2 silicon area and dissipating 9.14 mW from a 1.2-V supply with the synthesized digital calibration circuits included. The third work is an 8-bit, 600-MS/s, 10-way time-interleaved SAR ADC array fabricated in 0.13-μm CMOS process. This work employs an adaptive digital equalization approach to calibrate both intra-channel nonlinearities and inter-channel mismatch errors. The prototype chip achieves 47.4-dB SNDR, 63.6-dB SFDR, less than 0.30-LSB differential nonlinearity (DNL), and less than 0.23-LSB integral nonlinearity (INL). The ADC array occupies an active area of 1.35 mm2 and dissipates 30.3 mW, including synthesized digital calibration circuits and an on-chip dual-loop delay-locked loop (DLL) for clock generation and synchronization.","Item withdrawn by Mark Zulauf (zulauf@illinois.edu) on 2010-11-30T20:41:29Z Item was in collections: University of Illinois Theses & Dissertations (ID: 1) No. of bitstreams: 2 Liu_Wenbo.doc: 31347712 bytes, checksum: f20a1854de58c2dc7aad4c4b48da5c1c (MD5) Liu_Wenbo.pdf: 8643612 bytes, checksum: f5f48c639529d0eaab79e1854dbceff0 (MD5)","Made available in DSpace on 2011-01-21T22:52:11Z (GMT). No. of bitstreams: 3 Liu_Wenbo.pdf: 8643551 bytes, checksum: 7a8c1b846835a0230436dc440d674986 (MD5) Liu_Wenbo.doc: 31347712 bytes, checksum: f20a1854de58c2dc7aad4c4b48da5c1c (MD5) license.txt: 4056 bytes, checksum: b0d0e7abac09a6248094f5991ccf1130 (MD5)","Item marked as restricted to the 'Administrator' Group (id=1) by William Ingram (wingram2@illinois.edu) on 2011-01-21T22:53:56Z Item is restricted until 2013-01-21T22:53:34Z","Item reinstated by Sarah Shreeves (sshreeve@illinois.edu) on 2013-01-22T11:00:16Z Item was in collections: University of Illinois Dissertations and Theses (ID: 204) Dissertations and Theses - Electrical and Computer Engineering (ID: 446) No. of bitstreams: 4 Liu_Wenbo.pdf.txt: 164901 bytes, checksum: a02f3820a050b1d6004e944d8c659443 (MD5) Liu_Wenbo.pdf: 8643551 bytes, checksum: 7a8c1b846835a0230436dc440d674986 (MD5) Liu_Wenbo.doc: 31347712 bytes, checksum: f20a1854de58c2dc7aad4c4b48da5c1c (MD5) license.txt: 4056 bytes, checksum: b0d0e7abac09a6248094f5991ccf1130 (MD5)","Item released from any restrictions by Sarah Shreeves (sshreeve@illinois.edu) on 2013-01-22T11:00:16Z"]},{"key":"dc:title","label":"Title","values":["Low-power high-performance SAR ADC design with digital calibration techniques"]}]}],"canonical_facts":{"dc:contributor":["Chiu, Yun","Shanbhag, Naresh R.","Rosenbaum, Elyse","Singer, Andrew C."],"dc:creator":["Liu, Wenbo"],"dc:date":["2011-01-21T22:52:11Z","2013-01-22T11:00:16Z","2010-12"],"dc:description":["This dissertation presents the design of three high-performance successive-approximation-register (SAR) analog-to-digital converters (ADCs) using distinct digital background calibration techniques under the framework of a generalized code-domain linear equalizer. These digital calibration techniques effectively and efficiently remove the static mismatch errors in the analog-to-digital (A/D) conversion. They enable aggressive scaling of the capacitive digital-to-analog converter (DAC), which also serves as sampling capacitor, to the kT/C limit. As a result, outstanding conversion linearity, high signal-to-noise ratio (SNR), high conversion speed, robustness, superb energy efficiency, and minimal chip-area are accomplished simultaneously. The first design is a 12-bit 22.5/45-MS/s SAR ADC in 0.13-μm CMOS process. It employs a perturbation-based calibration based on the superposition property of linear systems to digitally correct the capacitor mismatch error in the weighted DAC. With 3.0-mW power dissipation at a 1.2-V power supply and a 22.5-MS/s sample rate, it achieves a 71.1-dB signal-to-noise-plus-distortion ratio (SNDR), and a 94.6-dB spurious free dynamic range (SFDR). At Nyquist frequency, the conversion figure of merit (FoM) is 50.8 fJ/conversion step, the best FoM up to date (2010) for 12-bit ADCs. The SAR ADC core occupies 0.06 mm2, while the estimated area the calibration circuits is 0.03 mm2. The second proposed digital calibration technique is a bit-wise-correlation-based digital calibration. It utilizes the statistical independence of an injected pseudo-random signal and the input signal to correct the DAC mismatch in SAR ADCs. This idea is experimentally verified in a 12-bit 37-MS/s SAR ADC fabricated in 65-nm CMOS implemented by Pingli Huang. This prototype chip achieves a 70.23-dB peak SNDR and an 81.02-dB peak SFDR, while occupying 0.12-mm2 silicon area and dissipating 9.14 mW from a 1.2-V supply with the synthesized digital calibration circuits included. The third work is an 8-bit, 600-MS/s, 10-way time-interleaved SAR ADC array fabricated in 0.13-μm CMOS process. This work employs an adaptive digital equalization approach to calibrate both intra-channel nonlinearities and inter-channel mismatch errors. The prototype chip achieves 47.4-dB SNDR, 63.6-dB SFDR, less than 0.30-LSB differential nonlinearity (DNL), and less than 0.23-LSB integral nonlinearity (INL). The ADC array occupies an active area of 1.35 mm2 and dissipates 30.3 mW, including synthesized digital calibration circuits and an on-chip dual-loop delay-locked loop (DLL) for clock generation and synchronization.","Item withdrawn by Mark Zulauf (zulauf@illinois.edu) on 2010-11-30T20:41:29Z Item was in collections: University of Illinois Theses & Dissertations (ID: 1) No. of bitstreams: 2 Liu_Wenbo.doc: 31347712 bytes, checksum: f20a1854de58c2dc7aad4c4b48da5c1c (MD5) Liu_Wenbo.pdf: 8643612 bytes, checksum: f5f48c639529d0eaab79e1854dbceff0 (MD5)","Made available in DSpace on 2011-01-21T22:52:11Z (GMT). No. of bitstreams: 3 Liu_Wenbo.pdf: 8643551 bytes, checksum: 7a8c1b846835a0230436dc440d674986 (MD5) Liu_Wenbo.doc: 31347712 bytes, checksum: f20a1854de58c2dc7aad4c4b48da5c1c (MD5) license.txt: 4056 bytes, checksum: b0d0e7abac09a6248094f5991ccf1130 (MD5)","Item marked as restricted to the 'Administrator' Group (id=1) by William Ingram (wingram2@illinois.edu) on 2011-01-21T22:53:56Z Item is restricted until 2013-01-21T22:53:34Z","Item reinstated by Sarah Shreeves (sshreeve@illinois.edu) on 2013-01-22T11:00:16Z Item was in collections: University of Illinois Dissertations and Theses (ID: 204) Dissertations and Theses - Electrical and Computer Engineering (ID: 446) No. of bitstreams: 4 Liu_Wenbo.pdf.txt: 164901 bytes, checksum: a02f3820a050b1d6004e944d8c659443 (MD5) Liu_Wenbo.pdf: 8643551 bytes, checksum: 7a8c1b846835a0230436dc440d674986 (MD5) Liu_Wenbo.doc: 31347712 bytes, checksum: f20a1854de58c2dc7aad4c4b48da5c1c (MD5) license.txt: 4056 bytes, checksum: b0d0e7abac09a6248094f5991ccf1130 (MD5)","Item released from any restrictions by Sarah Shreeves (sshreeve@illinois.edu) on 2013-01-22T11:00:16Z"],"dc:identifier":["http://hdl.handle.net/2142/18623"],"dc:language":["en"],"dc:rights":["Copyright 2010 Wenbo Liu"],"dc:subject":["successive-approximation-register (SAR) analog-to-digital converters (ADC)","redundancy","sub-radix-2","Nonlinearity","digital calibration","linear equalizer","generalized linear equalizer","perturbation","bit-wise correlation","channel mismatch","time-interleaved analog-to-digital converters (ADC)"],"dc:title":["Low-power high-performance SAR ADC design with digital calibration techniques"],"thesis:degree_discipline":["Electrical & Computer Engr"],"thesis:degree_level":["Dissertation"],"thesis:degree_name":["Ph.D."],"thesis:institution_name":["University of Illinois at Urbana-Champaign"]},"updated_at":"2026-07-22T22:25:11Z"}