{"id":{"repo_id":"uiuc","oai_identifier":"oai:www.ideals.illinois.edu:2142/18462"},"canonical_url":"https://search.dev.ndltd.org/etd/uiuc/oai:www.ideals.illinois.edu:2142/18462","repository":{"repo_id":"uiuc","name":"University of Illinois - Urbana-Champaign","base_url":"https://www.ideals.illinois.edu/oai-pmh"},"display":{"title":"New strategies for PCB routing","abstract":"As IC technology advances rapidly, the dimensions of packages and PCBs are decreasing while the pin counts and routing layers keep increasing. Today, a high-performance PCB usually contains thousands of pins and more than ten signal layers. Moreover, the manufacturing constraints require all nets to be routed in the planar fashion and the designer requires nets in the same bus to be routed together without any other net. All these factors pose new challenges for the PCB routing problem, making the PCB routing so difficult that no commercial CAD software can provide an automatic solution. Today, all high-end circuit boards are routed manually, in a time-consuming manner. In this dissertation, we present new strategies for automatic PCB routing. In particular, we present novel algorithms for bus sequencing, pin assignment, bus planning, bus escape, and escape routing.","abstract_html":"As IC technology advances rapidly, the dimensions of packages and PCBs are decreasing while the pin counts and routing layers keep increasing. Today, a high-performance PCB usually contains thousands of pins and more than ten signal layers. Moreover, the manufacturing constraints require all nets to be routed in the planar fashion and the designer requires nets in the same bus to be routed together without any other net. All these factors pose new challenges for the PCB routing problem, making the PCB routing so difficult that no commercial CAD software can provide an automatic solution. Today, all high-end circuit boards are routed manually, in a time-consuming manner. In this dissertation, we present new strategies for automatic PCB routing. In particular, we present novel algorithms for bus sequencing, pin assignment, bus planning, bus escape, and escape routing.","abstract_has_math":false,"creators":["Kong, Hui"],"institution":"University of Illinois at Urbana-Champaign","degree_name":"Ph.D.","degree_level":"Dissertation","degree_discipline":"Electrical & Computer Engr","degree_department":null,"school":null,"contributors":["Wong, Martin D.F.","Patel, Sanjay J.","Chen, Deming","Ozdal, Muhammet Mustafa"],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2011,"date_issued":"2011-01-14T22:51:37Z","date_published":"2011-01-14T22:51:37Z","updated_at":"2026-07-22T22:25:11Z","subjects":["Algorithms","Circuits","Printed Circuit Board (PCB) Routing"],"languages":["en"],"rights":["Copyright 2010 Hui Kong"],"rights_urls":[],"identifier_entries":[]},"links":{"outbound_url":"http://hdl.handle.net/2142/18462","outbound_label":"Handle","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Wong, Martin D.F.","Patel, Sanjay J.","Chen, Deming","Ozdal, Muhammet Mustafa"]},{"key":"dc:creator","label":"Author","values":["Kong, Hui"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2011-01-14T22:51:37Z","2010-12"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Electrical & Computer Engr"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Dissertation"]},{"key":"thesis:degree_name","label":"Degree Name","values":["Ph.D."]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["University of Illinois at Urbana-Champaign"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Algorithms","Circuits","Printed Circuit Board (PCB) Routing"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language","label":"Dc Language","values":["en"]},{"key":"dc:rights","label":"Dc Rights","values":["Copyright 2010 Hui Kong"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["http://hdl.handle.net/2142/18462"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["As IC technology advances rapidly, the dimensions of packages and PCBs are decreasing while the pin counts and routing layers keep increasing. Today, a high-performance PCB usually contains thousands of pins and more than ten signal layers. Moreover, the manufacturing constraints require all nets to be routed in the planar fashion and the designer requires nets in the same bus to be routed together without any other net. All these factors pose new challenges for the PCB routing problem, making the PCB routing so difficult that no commercial CAD software can provide an automatic solution. Today, all high-end circuit boards are routed manually, in a time-consuming manner. In this dissertation, we present new strategies for automatic PCB routing. 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All these factors pose new challenges for the PCB routing problem, making the PCB routing so difficult that no commercial CAD software can provide an automatic solution. Today, all high-end circuit boards are routed manually, in a time-consuming manner. In this dissertation, we present new strategies for automatic PCB routing. In particular, we present novel algorithms for bus sequencing, pin assignment, bus planning, bus escape, and escape routing.","Item withdrawn by Mark Zulauf (zulauf@illinois.edu) on 2010-11-19T13:54:42Z Item was in collections: University of Illinois Theses & Dissertations (ID: 1) No. of bitstreams: 1 Kong_Hui.pdf: 4210288 bytes, checksum: af0af12c153465e005bc33235d365fcb (MD5)","Made available in DSpace on 2011-01-14T22:51:37Z (GMT). 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