{"id":{"repo_id":"uiuc","oai_identifier":"oai:www.ideals.illinois.edu:2142/18360"},"canonical_url":"https://search.dev.ndltd.org/etd/uiuc/oai:www.ideals.illinois.edu:2142/18360","repository":{"repo_id":"uiuc","name":"University of Illinois - Urbana-Champaign","base_url":"https://www.ideals.illinois.edu/oai-pmh"},"display":{"title":"Topology Optimization with Unstructured Meshes on Graphics Processing Units (GPUs)","abstract":"The present work investigates the feasibility of nite element methods and topology optimization for unstructured meshes in massively parallel computer architectures, more speci cally on Graphics Processing Units or GPUs. Algorithms for every step in these methods are proposed and benchmarked with varied results. The ultimate goal of this work is to speed up the topology optimization process by means of parallel computing using o -the-shelf hardware. To further facilitate future application and deployment, a transparent massively parallel topology optimization code was written and tested. Examples are compared with both, a standard sequential version of the code, and a massively parallel version to better illustrate the advantages and disadvantages of this approach.","abstract_html":"The present work investigates the feasibility of nite element methods and topology optimization for unstructured meshes in massively parallel computer architectures, more speci cally on Graphics Processing Units or GPUs. Algorithms for every step in these methods are proposed and benchmarked with varied results. The ultimate goal of this work is to speed up the topology optimization process by means of parallel computing using o -the-shelf hardware. To further facilitate future application and deployment, a transparent massively parallel topology optimization code was written and tested. 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