{"id":{"repo_id":"uiuc","oai_identifier":"oai:www.ideals.illinois.edu:2142/18272"},"canonical_url":"https://search.dev.ndltd.org/etd/uiuc/oai:www.ideals.illinois.edu:2142/18272","repository":{"repo_id":"uiuc","name":"University of Illinois - Urbana-Champaign","base_url":"https://www.ideals.illinois.edu/oai-pmh"},"display":{"title":"Hybrid coherence for scalable multicore architectures","abstract":"Made available in DSpace on 2011-01-14T22:43:29Z (GMT). No. of bitstreams: 2 Kelm_John.pdf: 2626023 bytes, checksum: 069d102e87802f19ba796da9758e8be9 (MD5) license.txt: 4057 bytes, checksum: 83ce7b997e74195078c3d8fca669fdd2 (MD5)","abstract_html":"Made available in DSpace on 2011-01-14T22:43:29Z (GMT). No. of bitstreams: 2 Kelm_John.pdf: 2626023 bytes, checksum: 069d102e87802f19ba796da9758e8be9 (MD5) license.txt: 4057 bytes, checksum: 83ce7b997e74195078c3d8fca669fdd2 (MD5)","abstract_has_math":false,"creators":["Kelm, John H."],"institution":"University of Illinois at Urbana-Champaign","degree_name":"Ph.D.","degree_level":"Dissertation","degree_discipline":"Electrical & Computer Engr","degree_department":null,"school":null,"contributors":["Lumetta, Steven S.","Frank, Matthew I.","Chen, Deming","Patel, Sanjay J."],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2011,"date_issued":"2011-01-14T22:43:29Z","date_published":"2011-01-14T22:43:29Z","updated_at":"2026-07-22T22:25:11Z","subjects":["Accelerator architecture","hybrid architectures","memory model","cache coherence"],"languages":["en"],"rights":["Copyright 2010 John H. Kelm"],"rights_urls":[],"identifier_entries":[]},"links":{"outbound_url":"http://hdl.handle.net/2142/18272","outbound_label":"Handle","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Lumetta, Steven S.","Frank, Matthew I.","Chen, Deming","Patel, Sanjay J."]},{"key":"dc:creator","label":"Author","values":["Kelm, John H."]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2011-01-14T22:43:29Z","2010-12"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Electrical & Computer Engr"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Dissertation"]},{"key":"thesis:degree_name","label":"Degree Name","values":["Ph.D."]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["University of Illinois at Urbana-Champaign"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Accelerator architecture","hybrid architectures","memory model","cache coherence"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language","label":"Dc Language","values":["en"]},{"key":"dc:rights","label":"Dc Rights","values":["Copyright 2010 John H. Kelm"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["http://hdl.handle.net/2142/18272"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["Made available in DSpace on 2011-01-14T22:43:29Z (GMT). No. of bitstreams: 2 Kelm_John.pdf: 2626023 bytes, checksum: 069d102e87802f19ba796da9758e8be9 (MD5) license.txt: 4057 bytes, checksum: 83ce7b997e74195078c3d8fca669fdd2 (MD5)","This work describes a cache architecture and memory model for 1000+ core microprocessors. Our approach exploits workload characteristics and programming model assumptions to build a hybrid memory model that incorporates features from both software-managed coherence schemes and hardware cache coherence. The goal is to achieve the scalability found in compute accelerators, which support relaxed ordering of memory operations and programmer-managed coherence, while providing a programming interface that is akin to the strongly ordered cache coherent memory models found in general-purpose multicore processors today. The research presented in this dissertation supports the following thesis: To be scalable and programmable, future multicore systems require a cached, single-address space memory hierarchy. A hybrid software/hardware approach to coherence management is required to support such a memory hierarchy in 1000+ core processors and is achievable only by leveraging the characteristics of target applications and system software. We motivate a hybrid memory model and present our approach to addressing the challenges facing such a model. We discuss and evaluate a scalable 1024-core architecture, workloads that we see as targets for such an architecture, a memory model that relies on software management of coherence, and scalable hardware coherence schemes. Using these components, we develop the software and hardware support for a hybrid memory model. We demonstrate that our techniques can be used to reduce hardware design complexity, to increase software scalability, or to combine the two.","Item withdrawn by Mark Zulauf (zulauf@illinois.edu) on 2010-11-23T19:00:22Z Item was in collections: University of Illinois Theses & Dissertations (ID: 1) No. of bitstreams: 1 kelm-20101122.pdf: 2626023 bytes, checksum: 069d102e87802f19ba796da9758e8be9 (MD5)"]},{"key":"dc:title","label":"Title","values":["Hybrid coherence for scalable multicore architectures"]}]}],"canonical_facts":{"dc:contributor":["Lumetta, Steven S.","Frank, Matthew I.","Chen, Deming","Patel, Sanjay J."],"dc:creator":["Kelm, John H."],"dc:date":["2011-01-14T22:43:29Z","2010-12"],"dc:description":["Made available in DSpace on 2011-01-14T22:43:29Z (GMT). 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A hybrid software/hardware approach to coherence management is required to support such a memory hierarchy in 1000+ core processors and is achievable only by leveraging the characteristics of target applications and system software. We motivate a hybrid memory model and present our approach to addressing the challenges facing such a model. We discuss and evaluate a scalable 1024-core architecture, workloads that we see as targets for such an architecture, a memory model that relies on software management of coherence, and scalable hardware coherence schemes. Using these components, we develop the software and hardware support for a hybrid memory model. We demonstrate that our techniques can be used to reduce hardware design complexity, to increase software scalability, or to combine the two.","Item withdrawn by Mark Zulauf (zulauf@illinois.edu) on 2010-11-23T19:00:22Z Item was in collections: University of Illinois Theses & Dissertations (ID: 1) No. of bitstreams: 1 kelm-20101122.pdf: 2626023 bytes, checksum: 069d102e87802f19ba796da9758e8be9 (MD5)"],"dc:identifier":["http://hdl.handle.net/2142/18272"],"dc:language":["en"],"dc:rights":["Copyright 2010 John H. Kelm"],"dc:subject":["Accelerator architecture","hybrid architectures","memory model","cache coherence"],"dc:title":["Hybrid coherence for scalable multicore architectures"],"thesis:degree_discipline":["Electrical & Computer Engr"],"thesis:degree_level":["Dissertation"],"thesis:degree_name":["Ph.D."],"thesis:institution_name":["University of Illinois at Urbana-Champaign"]},"updated_at":"2026-07-22T22:25:11Z"}