{"id":{"repo_id":"uiuc","oai_identifier":"oai:www.ideals.illinois.edu:2142/16496"},"canonical_url":"https://search.dev.ndltd.org/etd/uiuc/oai:www.ideals.illinois.edu:2142/16496","repository":{"repo_id":"uiuc","name":"University of Illinois - Urbana-Champaign","base_url":"https://www.ideals.illinois.edu/oai-pmh"},"display":{"title":"Full chip modeling for predictive simulation of charged device model electrostatic discharge events","abstract":"With downscaling of device dimensions in integrated circuits (ICs), the risk of circuit failure due to electrostatic discharge (ESD) is increasing. In particular, the increased usage of automated handlers is causing charged device model (CDM) ESD induced failures to become more prominent. Gate oxide failure is the primary signature of CDM ESD. During CDM, the IC is the source as well as the path for the static charge. Therefore, it is important to include the circuit elements representing the package, ESD circuits and the silicon substrate of the packaged ICs. Power domain crossing circuits, also known as internal I/Os, are susceptible to gate oxide damage during CDM events. In this thesis, circuit-level simulations of internal I/O circuits are used to elucidate the roles of the package, power clamp placement, anti-parallel diode placement and decoupling capacitors in determining the amount of stress at the internal I/O circuits. This thesis will also provide design recommendations for preventing CDM failures in the internal I/O circuits.","abstract_html":"With downscaling of device dimensions in integrated circuits (ICs), the risk of circuit failure due to electrostatic discharge (ESD) is increasing. In particular, the increased usage of automated handlers is causing charged device model (CDM) ESD induced failures to become more prominent. Gate oxide failure is the primary signature of CDM ESD. During CDM, the IC is the source as well as the path for the static charge. Therefore, it is important to include the circuit elements representing the package, ESD circuits and the silicon substrate of the packaged ICs. Power domain crossing circuits, also known as internal I/Os, are susceptible to gate oxide damage during CDM events. In this thesis, circuit-level simulations of internal I/O circuits are used to elucidate the roles of the package, power clamp placement, anti-parallel diode placement and decoupling capacitors in determining the amount of stress at the internal I/O circuits. This thesis will also provide design recommendations for preventing CDM failures in the internal I/O circuits.","abstract_has_math":false,"creators":["Shukla, Vrashank G."],"institution":"University of Illinois at Urbana-Champaign","degree_name":"M.S.","degree_level":"Thesis","degree_discipline":"Electrical & Computer Engr","degree_department":null,"school":null,"contributors":["Rosenbaum, Elyse"],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2010,"date_issued":"2010-06-22T19:46:40Z","date_published":"2010-06-22T19:46:40Z","updated_at":"2026-07-22T22:25:09Z","subjects":["Internal I/O","Electrostatic discharge (ESD)","Charged device model (CDM)","Transient Simulation","Anti-parallel diodes"],"languages":["en"],"rights":["Copyright 2010 Vrashank G. Shukla"],"rights_urls":[],"identifier_entries":[]},"links":{"outbound_url":"http://hdl.handle.net/2142/16496","outbound_label":"Handle","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Rosenbaum, Elyse"]},{"key":"dc:creator","label":"Author","values":["Shukla, Vrashank G."]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2010-06-22T19:46:40Z","2010-5"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Electrical & Computer Engr"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Thesis"]},{"key":"thesis:degree_name","label":"Degree Name","values":["M.S."]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["University of Illinois at Urbana-Champaign"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Internal I/O","Electrostatic discharge (ESD)","Charged device model (CDM)","Transient Simulation","Anti-parallel diodes"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language","label":"Dc Language","values":["en"]},{"key":"dc:rights","label":"Dc Rights","values":["Copyright 2010 Vrashank G. Shukla"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["http://hdl.handle.net/2142/16496"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["With downscaling of device dimensions in integrated circuits (ICs), the risk of circuit failure due to electrostatic discharge (ESD) is increasing. In particular, the increased usage of automated handlers is causing charged device model (CDM) ESD induced failures to become more prominent. Gate oxide failure is the primary signature of CDM ESD. During CDM, the IC is the source as well as the path for the static charge. Therefore, it is important to include the circuit elements representing the package, ESD circuits and the silicon substrate of the packaged ICs. Power domain crossing circuits, also known as internal I/Os, are susceptible to gate oxide damage during CDM events. In this thesis, circuit-level simulations of internal I/O circuits are used to elucidate the roles of the package, power clamp placement, anti-parallel diode placement and decoupling capacitors in determining the amount of stress at the internal I/O circuits. This thesis will also provide design recommendations for preventing CDM failures in the internal I/O circuits.","Item withdrawn by Mark Zulauf (zulauf@illinois.edu) on 2010-04-26T21:29:14Z Item was in collections: University of Illinois Theses & Dissertations (ID: 1) No. of bitstreams: 2 Shukla_Vrashank.docx: 1533366 bytes, checksum: 54bd9f85863030dd708dbaa0089901ec (MD5) Shukla_Vrashank.pdf: 1436772 bytes, checksum: fc267d4e110dd7a104017ca97e4d001d (MD5)","Made available in DSpace on 2010-06-22T19:46:40Z (GMT). No. of bitstreams: 3 Shukla_Vrashank.docx: 1533366 bytes, checksum: 54bd9f85863030dd708dbaa0089901ec (MD5) Shukla_Vrashank.pdf: 1436772 bytes, checksum: fc267d4e110dd7a104017ca97e4d001d (MD5) license.txt: 4065 bytes, checksum: df26ef025c254bf4f0810b50db541be2 (MD5)"]},{"key":"dc:title","label":"Title","values":["Full chip modeling for predictive simulation of charged device model electrostatic discharge events"]}]}],"canonical_facts":{"dc:contributor":["Rosenbaum, Elyse"],"dc:creator":["Shukla, Vrashank G."],"dc:date":["2010-06-22T19:46:40Z","2010-5"],"dc:description":["With downscaling of device dimensions in integrated circuits (ICs), the risk of circuit failure due to electrostatic discharge (ESD) is increasing. In particular, the increased usage of automated handlers is causing charged device model (CDM) ESD induced failures to become more prominent. Gate oxide failure is the primary signature of CDM ESD. During CDM, the IC is the source as well as the path for the static charge. Therefore, it is important to include the circuit elements representing the package, ESD circuits and the silicon substrate of the packaged ICs. Power domain crossing circuits, also known as internal I/Os, are susceptible to gate oxide damage during CDM events. In this thesis, circuit-level simulations of internal I/O circuits are used to elucidate the roles of the package, power clamp placement, anti-parallel diode placement and decoupling capacitors in determining the amount of stress at the internal I/O circuits. This thesis will also provide design recommendations for preventing CDM failures in the internal I/O circuits.","Item withdrawn by Mark Zulauf (zulauf@illinois.edu) on 2010-04-26T21:29:14Z Item was in collections: University of Illinois Theses & Dissertations (ID: 1) No. of bitstreams: 2 Shukla_Vrashank.docx: 1533366 bytes, checksum: 54bd9f85863030dd708dbaa0089901ec (MD5) Shukla_Vrashank.pdf: 1436772 bytes, checksum: fc267d4e110dd7a104017ca97e4d001d (MD5)","Made available in DSpace on 2010-06-22T19:46:40Z (GMT). No. of bitstreams: 3 Shukla_Vrashank.docx: 1533366 bytes, checksum: 54bd9f85863030dd708dbaa0089901ec (MD5) Shukla_Vrashank.pdf: 1436772 bytes, checksum: fc267d4e110dd7a104017ca97e4d001d (MD5) license.txt: 4065 bytes, checksum: df26ef025c254bf4f0810b50db541be2 (MD5)"],"dc:identifier":["http://hdl.handle.net/2142/16496"],"dc:language":["en"],"dc:rights":["Copyright 2010 Vrashank G. Shukla"],"dc:subject":["Internal I/O","Electrostatic discharge (ESD)","Charged device model (CDM)","Transient Simulation","Anti-parallel diodes"],"dc:title":["Full chip modeling for predictive simulation of charged device model electrostatic discharge events"],"thesis:degree_discipline":["Electrical & Computer Engr"],"thesis:degree_level":["Thesis"],"thesis:degree_name":["M.S."],"thesis:institution_name":["University of Illinois at Urbana-Champaign"]},"updated_at":"2026-07-22T22:25:09Z"}