{"id":{"repo_id":"uiuc","oai_identifier":"oai:www.ideals.illinois.edu:2142/132812"},"canonical_url":"https://search.dev.ndltd.org/etd/uiuc/oai:www.ideals.illinois.edu:2142/132812","repository":{"repo_id":"uiuc","name":"University of Illinois - Urbana-Champaign","base_url":"https://www.ideals.illinois.edu/oai-pmh"},"display":{"title":"Development of electrical and optical devices for next generation high-speed optical interconnects","abstract":"Rapid advances in AI, LLMs, and IoT are pushing data traffic toward >1.6 Tb/s optical links with much lower energy per bit. VCSEL based multichannel transceivers are one of the most cost- and power-efficient choice for short-reach interconnects, but further scaling is limited by modal dispersion in multimode VCSELs and bandwidth/power ceilings in both VCSELs and silicon driver/control ICs as per-lane rates exceed 200 Gb/s. Accordingly, overcoming optical limitations requires both aggressive aperture scale-down and targeted process advancements in VCSEL fabrication. The electrical limits motivate using higher-speed electronic devices such as InP based Type-II DHBTs. Meanwhile, cryogenic and quantum computing demand ultra-efficient links bridging cryogenic processors to room-temperature peripheral electronics; Cryo-VCSELs offer ~100 GHz bandwidth at few milliampere bias range and enable >448-Gb/s PAM-4 operation but require tighter process control and microcavity-scaling insight. This thesis advances two fronts: first, a wafer-scale, OpenCV-based automated oxide-aperture measurement method that replaces manual ImageJ, enabling full-wafer oxidation maps at high throughput and exposing critical nonuniformities for <3-µm apertures; and, second, a quantitative study of emitter-ledge effects in sub-micron InP/GaAsSb Type-II DHBTs, showing a 160-nm ledge can more than double DC current gain β by suppressing surface recombination, but with trade-offs in ideality factor, yield, base resistance, and fT/fmax. Together, these results provide the process capability and device understanding needed to co-optimize Cryo-VCSEL sources and InP-DHBT electronics for fJ/bit-class, long-reach optical interconnects in hybrid-temperature computing systems.","abstract_html":"Rapid advances in AI, LLMs, and IoT are pushing data traffic toward &gt;1.6 Tb/s optical links with much lower energy per bit. VCSEL based multichannel transceivers are one of the most cost- and power-efficient choice for short-reach interconnects, but further scaling is limited by modal dispersion in multimode VCSELs and bandwidth/power ceilings in both VCSELs and silicon driver/control ICs as per-lane rates exceed 200 Gb/s. Accordingly, overcoming optical limitations requires both aggressive aperture scale-down and targeted process advancements in VCSEL fabrication. The electrical limits motivate using higher-speed electronic devices such as InP based Type-II DHBTs. Meanwhile, cryogenic and quantum computing demand ultra-efficient links bridging cryogenic processors to room-temperature peripheral electronics; Cryo-VCSELs offer ~100 GHz bandwidth at few milliampere bias range and enable &gt;448-Gb/s PAM-4 operation but require tighter process control and microcavity-scaling insight. This thesis advances two fronts: first, a wafer-scale, OpenCV-based automated oxide-aperture measurement method that replaces manual ImageJ, enabling full-wafer oxidation maps at high throughput and exposing critical nonuniformities for &lt;3-µm apertures; and, second, a quantitative study of emitter-ledge effects in sub-micron InP/GaAsSb Type-II DHBTs, showing a 160-nm ledge can more than double DC current gain β by suppressing surface recombination, but with trade-offs in ideality factor, yield, base resistance, and fT/fmax. Together, these results provide the process capability and device understanding needed to co-optimize Cryo-VCSEL sources and InP-DHBT electronics for fJ/bit-class, long-reach optical interconnects in hybrid-temperature computing systems.","abstract_has_math":false,"creators":["Liu, Zetai"],"institution":"University of Illinois Urbana-Champaign","degree_name":"M.S.","degree_level":"Thesis","degree_discipline":"Electrical & Computer Engr","degree_department":null,"school":null,"contributors":["Feng, Milton"],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2025,"date_issued":"2025-12","date_published":"2025-12","updated_at":"2026-07-22T22:25:07Z","subjects":["High Speed Data Com, VCSEL, HBT, Fabrication, Testing"],"languages":["en"],"rights":["Copyright 2025 Zetai Liu"],"rights_urls":[],"identifier_entries":[]},"links":{"outbound_url":"https://hdl.handle.net/2142/132812","outbound_label":"Handle","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Feng, Milton"]},{"key":"dc:creator","label":"Author","values":["Liu, Zetai"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2025-12","2025-12-10"]},{"key":"dc:type","label":"Dc Type","values":["text","Thesis"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Electrical & Computer Engr"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Thesis"]},{"key":"thesis:degree_name","label":"Degree Name","values":["M.S."]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["University of Illinois Urbana-Champaign"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["High Speed Data Com, VCSEL, HBT, Fabrication, Testing"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language","label":"Dc Language","values":["en"]},{"key":"dc:rights","label":"Dc Rights","values":["Copyright 2025 Zetai Liu"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["https://hdl.handle.net/2142/132812"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["Rapid advances in AI, LLMs, and IoT are pushing data traffic toward >1.6 Tb/s optical links with much lower energy per bit. VCSEL based multichannel transceivers are one of the most cost- and power-efficient choice for short-reach interconnects, but further scaling is limited by modal dispersion in multimode VCSELs and bandwidth/power ceilings in both VCSELs and silicon driver/control ICs as per-lane rates exceed 200 Gb/s. Accordingly, overcoming optical limitations requires both aggressive aperture scale-down and targeted process advancements in VCSEL fabrication. The electrical limits motivate using higher-speed electronic devices such as InP based Type-II DHBTs. Meanwhile, cryogenic and quantum computing demand ultra-efficient links bridging cryogenic processors to room-temperature peripheral electronics; Cryo-VCSELs offer ~100 GHz bandwidth at few milliampere bias range and enable >448-Gb/s PAM-4 operation but require tighter process control and microcavity-scaling insight. This thesis advances two fronts: first, a wafer-scale, OpenCV-based automated oxide-aperture measurement method that replaces manual ImageJ, enabling full-wafer oxidation maps at high throughput and exposing critical nonuniformities for <3-µm apertures; and, second, a quantitative study of emitter-ledge effects in sub-micron InP/GaAsSb Type-II DHBTs, showing a 160-nm ledge can more than double DC current gain β by suppressing surface recombination, but with trade-offs in ideality factor, yield, base resistance, and fT/fmax. Together, these results provide the process capability and device understanding needed to co-optimize Cryo-VCSEL sources and InP-DHBT electronics for fJ/bit-class, long-reach optical interconnects in hybrid-temperature computing systems.","Submission published under a 24 month embargo labeled 'Closed Access', the embargo will last until 2027-12-01","The student, Zetai Liu, accepted the attached license on 2025-12-10 at 14:12.","The student, Zetai Liu, submitted this Thesis for approval on 2025-12-10 at 14:19.","This Thesis was approved for publication on 2025-12-10 at 19:08.","DSpace SAF Submission Ingestion Package generated from Vireo submission #23126 on 2026-02-19 at 20:10:10"]},{"key":"dc:format","label":"Dc Format","values":["application/pdf"]},{"key":"dc:title","label":"Title","values":["Development of electrical and optical devices for next generation high-speed optical interconnects"]}]}],"canonical_facts":{"dc:contributor":["Feng, Milton"],"dc:creator":["Liu, Zetai"],"dc:date":["2025-12","2025-12-10"],"dc:description":["Rapid advances in AI, LLMs, and IoT are pushing data traffic toward >1.6 Tb/s optical links with much lower energy per bit. VCSEL based multichannel transceivers are one of the most cost- and power-efficient choice for short-reach interconnects, but further scaling is limited by modal dispersion in multimode VCSELs and bandwidth/power ceilings in both VCSELs and silicon driver/control ICs as per-lane rates exceed 200 Gb/s. Accordingly, overcoming optical limitations requires both aggressive aperture scale-down and targeted process advancements in VCSEL fabrication. The electrical limits motivate using higher-speed electronic devices such as InP based Type-II DHBTs. Meanwhile, cryogenic and quantum computing demand ultra-efficient links bridging cryogenic processors to room-temperature peripheral electronics; Cryo-VCSELs offer ~100 GHz bandwidth at few milliampere bias range and enable >448-Gb/s PAM-4 operation but require tighter process control and microcavity-scaling insight. This thesis advances two fronts: first, a wafer-scale, OpenCV-based automated oxide-aperture measurement method that replaces manual ImageJ, enabling full-wafer oxidation maps at high throughput and exposing critical nonuniformities for <3-µm apertures; and, second, a quantitative study of emitter-ledge effects in sub-micron InP/GaAsSb Type-II DHBTs, showing a 160-nm ledge can more than double DC current gain β by suppressing surface recombination, but with trade-offs in ideality factor, yield, base resistance, and fT/fmax. Together, these results provide the process capability and device understanding needed to co-optimize Cryo-VCSEL sources and InP-DHBT electronics for fJ/bit-class, long-reach optical interconnects in hybrid-temperature computing systems.","Submission published under a 24 month embargo labeled 'Closed Access', the embargo will last until 2027-12-01","The student, Zetai Liu, accepted the attached license on 2025-12-10 at 14:12.","The student, Zetai Liu, submitted this Thesis for approval on 2025-12-10 at 14:19.","This Thesis was approved for publication on 2025-12-10 at 19:08.","DSpace SAF Submission Ingestion Package generated from Vireo submission #23126 on 2026-02-19 at 20:10:10"],"dc:format":["application/pdf"],"dc:identifier":["https://hdl.handle.net/2142/132812"],"dc:language":["en"],"dc:rights":["Copyright 2025 Zetai Liu"],"dc:subject":["High Speed Data Com, VCSEL, HBT, Fabrication, Testing"],"dc:title":["Development of electrical and optical devices for next generation high-speed optical interconnects"],"dc:type":["text","Thesis"],"thesis:degree_discipline":["Electrical & Computer Engr"],"thesis:degree_level":["Thesis"],"thesis:degree_name":["M.S."],"thesis:institution_name":["University of Illinois Urbana-Champaign"]},"updated_at":"2026-07-22T22:25:07Z"}