{"id":{"repo_id":"uiuc","oai_identifier":"oai:www.ideals.illinois.edu:2142/132743"},"canonical_url":"https://search.dev.ndltd.org/etd/uiuc/oai:www.ideals.illinois.edu:2142/132743","repository":{"repo_id":"uiuc","name":"University of Illinois - Urbana-Champaign","base_url":"https://www.ideals.illinois.edu/oai-pmh"},"display":{"title":"In-situ impedance characterization for assessing SiC MOSFETs reliability","abstract":"This dissertation presents an in-situ and online impedance characterization circuit for condition monitoring (CM) of Silicon Carbide (SiC) MOSFETs. The core concept involves injecting a pre-adjusted high-frequency current (≥ 2 MHz) into the device and isolating the resulting voltage component induced by this injection. By applying algebraic operations, the drain-to-source impedance is characterized and separated into its sub-components: on-state resistance and package inductance. Accelerated aging experiments confirm that on-state resistance correlates with gate-oxide degradation, while bond-wire lift-off leads to a measurable increase in package inductance. The circuit is thus capable of simultaneously tracking both degradation modes. Its performance is validated through extensive experimental setups including impedance analyzers, network analysis, oscilloscope waveforms, and x-ray imaging. In addition, the thesis proposes a scalable and galvanically isolated solution for monitoring multiple SiC MOSFETs operating in complementary configurations, enabling integration into practical converter topologies. Gate-oxide degradation is evaluated using time-dependent dielectric breakdown testing, where gate-leakage current and on-state resistance are monitored. Results indicate that gate-leakage current remains in the sub-microampere range until the device fails abruptly, whereas on-state resistance exhibits a gradual increase due to growing trap concentration in the oxide. This makes on-state resistance a more practical precursor for early detection of gate-oxide degradation and preemptive device replacement. Bond-wires represent another critical point of failure in SiC MOSFETs, largely due to the mechanical mismatch between aluminum wires and the SiC substrate. Thermal cycling over a device’s lifetime can cause fatigue at the solder joint, eventually leading to bond-wire lift-off. Even with multiple parallel wires, failure of one increases stress on the remaining wires and accelerates degradation. Package inductance, primarily shaped by bond-wire layout, is a unique and temperature-independent indicator of bond-wire integrity. A lift-off changes the current distribution and results in a step increase in inductance. Although this principle was known, no in-situ method previously existed. This work introduces the first in-situ and online solution capable of measuring package inductance with high sensitivity—detecting changes as small as 10 pH with 99 % confidence—as well as milliohm-level changes in on-state resistance. Finally, the thesis presents a scalable, galvanically isolated monitoring solution tailored for complementary switch configurations commonly found in half-bridge, T-type, and neutral-point-clamp topologies. Instead of duplicating CM circuitry for each device, a single CM unit connects to complementary switches through a custom multi-port transformer. The proposed AC current-injection technique leverages the transformer windings for both current injection and voltage sensing. Because the transformer coils can float at arbitrary voltage levels, this system can monitor devices referenced to non-zero potentials. Electromagnetic design of a three-port transformer and a novel clamp-bias circuit are discussed in detail. The complete solution is experimentally validated on a SiC half-bridge operating at 800 V with 16 APP ripple current, successfully detecting individual bond-wire lift-off events on both high- and low-side devices.","abstract_html":"This dissertation presents an in-situ and online impedance characterization circuit for condition monitoring (CM) of Silicon Carbide (SiC) MOSFETs. The core concept involves injecting a pre-adjusted high-frequency current (≥ 2 MHz) into the device and isolating the resulting voltage component induced by this injection. By applying algebraic operations, the drain-to-source impedance is characterized and separated into its sub-components: on-state resistance and package inductance. Accelerated aging experiments confirm that on-state resistance correlates with gate-oxide degradation, while bond-wire lift-off leads to a measurable increase in package inductance. The circuit is thus capable of simultaneously tracking both degradation modes. Its performance is validated through extensive experimental setups including impedance analyzers, network analysis, oscilloscope waveforms, and x-ray imaging. In addition, the thesis proposes a scalable and galvanically isolated solution for monitoring multiple SiC MOSFETs operating in complementary configurations, enabling integration into practical converter topologies. Gate-oxide degradation is evaluated using time-dependent dielectric breakdown testing, where gate-leakage current and on-state resistance are monitored. Results indicate that gate-leakage current remains in the sub-microampere range until the device fails abruptly, whereas on-state resistance exhibits a gradual increase due to growing trap concentration in the oxide. This makes on-state resistance a more practical precursor for early detection of gate-oxide degradation and preemptive device replacement. Bond-wires represent another critical point of failure in SiC MOSFETs, largely due to the mechanical mismatch between aluminum wires and the SiC substrate. Thermal cycling over a device’s lifetime can cause fatigue at the solder joint, eventually leading to bond-wire lift-off. Even with multiple parallel wires, failure of one increases stress on the remaining wires and accelerates degradation. Package inductance, primarily shaped by bond-wire layout, is a unique and temperature-independent indicator of bond-wire integrity. A lift-off changes the current distribution and results in a step increase in inductance. Although this principle was known, no in-situ method previously existed. This work introduces the first in-situ and online solution capable of measuring package inductance with high sensitivity—detecting changes as small as 10 pH with 99 % confidence—as well as milliohm-level changes in on-state resistance. Finally, the thesis presents a scalable, galvanically isolated monitoring solution tailored for complementary switch configurations commonly found in half-bridge, T-type, and neutral-point-clamp topologies. Instead of duplicating CM circuitry for each device, a single CM unit connects to complementary switches through a custom multi-port transformer. The proposed AC current-injection technique leverages the transformer windings for both current injection and voltage sensing. Because the transformer coils can float at arbitrary voltage levels, this system can monitor devices referenced to non-zero potentials. Electromagnetic design of a three-port transformer and a novel clamp-bias circuit are discussed in detail. The complete solution is experimentally validated on a SiC half-bridge operating at 800 V with 16 APP ripple current, successfully detecting individual bond-wire lift-off events on both high- and low-side devices.","abstract_has_math":false,"creators":["Karakaya, Furkan"],"institution":"University of Illinois Urbana-Champaign","degree_name":"Ph.D.","degree_level":"Dissertation","degree_discipline":"Electrical & Computer Engr","degree_department":null,"school":null,"contributors":["Banerjee, Arijit","Donnal, John S.","Rakheja, Shaloo","Stillwell, Andrew R.","Sung, Woongje"],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2025,"date_issued":"2025-12","date_published":"2025-12","updated_at":"2026-07-22T22:25:07Z","subjects":["Power electronics","reliability","degradation","diagnostics","silicon carbide","SiC","MOSFET","condition monitoring","aging evaluation","gate oxide health","bond wire health","device health","in-situ","impedance characterization","current injection","analog circuits","high frequency","radio frequency","online estimation","on state resistance","package inductance","on state impedance","channel impedance","mosfet channel"],"languages":["en"],"rights":["Copyright 2025 Furkan Karakaya"],"rights_urls":[],"identifier_entries":[]},"links":{"outbound_url":"https://hdl.handle.net/2142/132743","outbound_label":"Handle","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Banerjee, Arijit","Donnal, John S.","Rakheja, Shaloo","Stillwell, Andrew R.","Sung, Woongje"]},{"key":"dc:creator","label":"Author","values":["Karakaya, Furkan"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2025-12","2025-09-30"]},{"key":"dc:type","label":"Dc Type","values":["text","Thesis"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Electrical & Computer Engr"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Dissertation"]},{"key":"thesis:degree_name","label":"Degree Name","values":["Ph.D."]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["University of Illinois Urbana-Champaign"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Power electronics","reliability","degradation","diagnostics","silicon carbide","SiC","MOSFET","condition monitoring","aging evaluation","gate oxide health","bond wire health","device health","in-situ","impedance characterization","current injection","analog circuits","high frequency","radio frequency","online estimation","on state resistance","package inductance","on state impedance","channel impedance","mosfet channel"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language","label":"Dc Language","values":["en"]},{"key":"dc:rights","label":"Dc Rights","values":["Copyright 2025 Furkan Karakaya"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["https://hdl.handle.net/2142/132743"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["This dissertation presents an in-situ and online impedance characterization circuit for condition monitoring (CM) of Silicon Carbide (SiC) MOSFETs. The core concept involves injecting a pre-adjusted high-frequency current (≥ 2 MHz) into the device and isolating the resulting voltage component induced by this injection. By applying algebraic operations, the drain-to-source impedance is characterized and separated into its sub-components: on-state resistance and package inductance. Accelerated aging experiments confirm that on-state resistance correlates with gate-oxide degradation, while bond-wire lift-off leads to a measurable increase in package inductance. The circuit is thus capable of simultaneously tracking both degradation modes. Its performance is validated through extensive experimental setups including impedance analyzers, network analysis, oscilloscope waveforms, and x-ray imaging. In addition, the thesis proposes a scalable and galvanically isolated solution for monitoring multiple SiC MOSFETs operating in complementary configurations, enabling integration into practical converter topologies. Gate-oxide degradation is evaluated using time-dependent dielectric breakdown testing, where gate-leakage current and on-state resistance are monitored. Results indicate that gate-leakage current remains in the sub-microampere range until the device fails abruptly, whereas on-state resistance exhibits a gradual increase due to growing trap concentration in the oxide. This makes on-state resistance a more practical precursor for early detection of gate-oxide degradation and preemptive device replacement. Bond-wires represent another critical point of failure in SiC MOSFETs, largely due to the mechanical mismatch between aluminum wires and the SiC substrate. Thermal cycling over a device’s lifetime can cause fatigue at the solder joint, eventually leading to bond-wire lift-off. Even with multiple parallel wires, failure of one increases stress on the remaining wires and accelerates degradation. Package inductance, primarily shaped by bond-wire layout, is a unique and temperature-independent indicator of bond-wire integrity. A lift-off changes the current distribution and results in a step increase in inductance. Although this principle was known, no in-situ method previously existed. This work introduces the first in-situ and online solution capable of measuring package inductance with high sensitivity—detecting changes as small as 10 pH with 99 % confidence—as well as milliohm-level changes in on-state resistance. Finally, the thesis presents a scalable, galvanically isolated monitoring solution tailored for complementary switch configurations commonly found in half-bridge, T-type, and neutral-point-clamp topologies. Instead of duplicating CM circuitry for each device, a single CM unit connects to complementary switches through a custom multi-port transformer. The proposed AC current-injection technique leverages the transformer windings for both current injection and voltage sensing. Because the transformer coils can float at arbitrary voltage levels, this system can monitor devices referenced to non-zero potentials. Electromagnetic design of a three-port transformer and a novel clamp-bias circuit are discussed in detail. The complete solution is experimentally validated on a SiC half-bridge operating at 800 V with 16 APP ripple current, successfully detecting individual bond-wire lift-off events on both high- and low-side devices.","Submission published under a 24 month embargo labeled 'Closed Access', the embargo will last until 2027-12-01","The student, Furkan Karakaya, accepted the attached license on 2025-09-28 at 20:16.","The student, Furkan Karakaya, submitted this Dissertation for approval on 2025-09-28 at 21:00.","This Dissertation was approved for publication on 2025-09-30 at 11:55.","DSpace SAF Submission Ingestion Package generated from Vireo submission #22816 on 2026-02-19 at 20:08:19"]},{"key":"dc:format","label":"Dc Format","values":["application/pdf"]},{"key":"dc:title","label":"Title","values":["In-situ impedance characterization for assessing SiC MOSFETs reliability"]}]}],"canonical_facts":{"dc:contributor":["Banerjee, Arijit","Donnal, John S.","Rakheja, Shaloo","Stillwell, Andrew R.","Sung, Woongje"],"dc:creator":["Karakaya, Furkan"],"dc:date":["2025-12","2025-09-30"],"dc:description":["This dissertation presents an in-situ and online impedance characterization circuit for condition monitoring (CM) of Silicon Carbide (SiC) MOSFETs. The core concept involves injecting a pre-adjusted high-frequency current (≥ 2 MHz) into the device and isolating the resulting voltage component induced by this injection. By applying algebraic operations, the drain-to-source impedance is characterized and separated into its sub-components: on-state resistance and package inductance. Accelerated aging experiments confirm that on-state resistance correlates with gate-oxide degradation, while bond-wire lift-off leads to a measurable increase in package inductance. The circuit is thus capable of simultaneously tracking both degradation modes. Its performance is validated through extensive experimental setups including impedance analyzers, network analysis, oscilloscope waveforms, and x-ray imaging. In addition, the thesis proposes a scalable and galvanically isolated solution for monitoring multiple SiC MOSFETs operating in complementary configurations, enabling integration into practical converter topologies. Gate-oxide degradation is evaluated using time-dependent dielectric breakdown testing, where gate-leakage current and on-state resistance are monitored. Results indicate that gate-leakage current remains in the sub-microampere range until the device fails abruptly, whereas on-state resistance exhibits a gradual increase due to growing trap concentration in the oxide. This makes on-state resistance a more practical precursor for early detection of gate-oxide degradation and preemptive device replacement. Bond-wires represent another critical point of failure in SiC MOSFETs, largely due to the mechanical mismatch between aluminum wires and the SiC substrate. Thermal cycling over a device’s lifetime can cause fatigue at the solder joint, eventually leading to bond-wire lift-off. Even with multiple parallel wires, failure of one increases stress on the remaining wires and accelerates degradation. Package inductance, primarily shaped by bond-wire layout, is a unique and temperature-independent indicator of bond-wire integrity. A lift-off changes the current distribution and results in a step increase in inductance. Although this principle was known, no in-situ method previously existed. This work introduces the first in-situ and online solution capable of measuring package inductance with high sensitivity—detecting changes as small as 10 pH with 99 % confidence—as well as milliohm-level changes in on-state resistance. Finally, the thesis presents a scalable, galvanically isolated monitoring solution tailored for complementary switch configurations commonly found in half-bridge, T-type, and neutral-point-clamp topologies. Instead of duplicating CM circuitry for each device, a single CM unit connects to complementary switches through a custom multi-port transformer. The proposed AC current-injection technique leverages the transformer windings for both current injection and voltage sensing. Because the transformer coils can float at arbitrary voltage levels, this system can monitor devices referenced to non-zero potentials. Electromagnetic design of a three-port transformer and a novel clamp-bias circuit are discussed in detail. The complete solution is experimentally validated on a SiC half-bridge operating at 800 V with 16 APP ripple current, successfully detecting individual bond-wire lift-off events on both high- and low-side devices.","Submission published under a 24 month embargo labeled 'Closed Access', the embargo will last until 2027-12-01","The student, Furkan Karakaya, accepted the attached license on 2025-09-28 at 20:16.","The student, Furkan Karakaya, submitted this Dissertation for approval on 2025-09-28 at 21:00.","This Dissertation was approved for publication on 2025-09-30 at 11:55.","DSpace SAF Submission Ingestion Package generated from Vireo submission #22816 on 2026-02-19 at 20:08:19"],"dc:format":["application/pdf"],"dc:identifier":["https://hdl.handle.net/2142/132743"],"dc:language":["en"],"dc:rights":["Copyright 2025 Furkan Karakaya"],"dc:subject":["Power electronics","reliability","degradation","diagnostics","silicon carbide","SiC","MOSFET","condition monitoring","aging evaluation","gate oxide health","bond wire health","device health","in-situ","impedance characterization","current injection","analog circuits","high frequency","radio frequency","online estimation","on state resistance","package inductance","on state impedance","channel impedance","mosfet channel"],"dc:title":["In-situ impedance characterization for assessing SiC MOSFETs reliability"],"dc:type":["text","Thesis"],"thesis:degree_discipline":["Electrical & Computer Engr"],"thesis:degree_level":["Dissertation"],"thesis:degree_name":["Ph.D."],"thesis:institution_name":["University of Illinois Urbana-Champaign"]},"updated_at":"2026-07-22T22:25:07Z"}