{"id":{"repo_id":"uiuc","oai_identifier":"oai:www.ideals.illinois.edu:2142/132701"},"canonical_url":"https://search.dev.ndltd.org/etd/uiuc/oai:www.ideals.illinois.edu:2142/132701","repository":{"repo_id":"uiuc","name":"University of Illinois - Urbana-Champaign","base_url":"https://www.ideals.illinois.edu/oai-pmh"},"display":{"title":"Demystifying CXL type-2 devices—with composable CXL-SSDS as a case study","abstract":"CXL is a PCIe-based interconnect that defines three protocols for three classes of devices, each with distinct capabilities. Commercial adoption has arrived first for CXL Type-3 devices, with CXL Type-2 devices emerging afterward—making it timely to clarify CXL Type-2 device’s capabilities and applications. We first examine three core CXL Type-2 device features: cache-coherent device accelerator to host memory, device accelerator to device memory, and host CPU to device memory accesses. We then introduce CXL-AnySSD, a composable, memory-semantic CXL-SSD that exploits hardware-managed device-to-host transfers in CXL Type-2 devices. By loosely coupling DRAM with commodity SSDs, CXL-AnySSD decouples capacity from performance, supports heterogeneous SSD choices, and removes OS-managed swap overheads. We implement a CXL-AnySSD prototype on a real CXL Type-2 device and show CXL-AnySSD improves end-to-end throughput by 2.3–6.2× over OS-managed SSD swap on a vector-database workload.","abstract_html":"CXL is a PCIe-based interconnect that defines three protocols for three classes of devices, each with distinct capabilities. Commercial adoption has arrived first for CXL Type-3 devices, with CXL Type-2 devices emerging afterward—making it timely to clarify CXL Type-2 device’s capabilities and applications. We first examine three core CXL Type-2 device features: cache-coherent device accelerator to host memory, device accelerator to device memory, and host CPU to device memory accesses. We then introduce CXL-AnySSD, a composable, memory-semantic CXL-SSD that exploits hardware-managed device-to-host transfers in CXL Type-2 devices. By loosely coupling DRAM with commodity SSDs, CXL-AnySSD decouples capacity from performance, supports heterogeneous SSD choices, and removes OS-managed swap overheads. We implement a CXL-AnySSD prototype on a real CXL Type-2 device and show CXL-AnySSD improves end-to-end throughput by 2.3–6.2× over OS-managed SSD swap on a vector-database workload.","abstract_has_math":false,"creators":["Zhou, Yang"],"institution":"University of Illinois Urbana-Champaign","degree_name":"M.S.","degree_level":"Thesis","degree_discipline":"Electrical & Computer Engr","degree_department":null,"school":null,"contributors":["Kim, Nam Sung"],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2025,"date_issued":"2025-12","date_published":"2025-12","updated_at":"2026-07-22T22:25:07Z","subjects":["Compute Express Link","Heterogeneous Computing"],"languages":["en"],"rights":["Copyright 2025 Yang Zhou"],"rights_urls":[],"identifier_entries":[]},"links":{"outbound_url":"https://hdl.handle.net/2142/132701","outbound_label":"Handle","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Kim, Nam Sung"]},{"key":"dc:creator","label":"Author","values":["Zhou, Yang"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2025-12","2025-12-09"]},{"key":"dc:type","label":"Dc Type","values":["text","Thesis"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Electrical & Computer Engr"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Thesis"]},{"key":"thesis:degree_name","label":"Degree Name","values":["M.S."]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["University of Illinois Urbana-Champaign"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Compute Express Link","Heterogeneous Computing"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language","label":"Dc Language","values":["en"]},{"key":"dc:rights","label":"Dc Rights","values":["Copyright 2025 Yang Zhou"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["https://hdl.handle.net/2142/132701"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["CXL is a PCIe-based interconnect that defines three protocols for three classes of devices, each with distinct capabilities. Commercial adoption has arrived first for CXL Type-3 devices, with CXL Type-2 devices emerging afterward—making it timely to clarify CXL Type-2 device’s capabilities and applications. We first examine three core CXL Type-2 device features: cache-coherent device accelerator to host memory, device accelerator to device memory, and host CPU to device memory accesses. We then introduce CXL-AnySSD, a composable, memory-semantic CXL-SSD that exploits hardware-managed device-to-host transfers in CXL Type-2 devices. By loosely coupling DRAM with commodity SSDs, CXL-AnySSD decouples capacity from performance, supports heterogeneous SSD choices, and removes OS-managed swap overheads. We implement a CXL-AnySSD prototype on a real CXL Type-2 device and show CXL-AnySSD improves end-to-end throughput by 2.3–6.2× over OS-managed SSD swap on a vector-database workload.","Submission published under a 24 month embargo labeled 'U of I Access', the embargo will last until 2027-12-01","The student, Yang Zhou, accepted the attached license on 2025-12-09 at 08:37.","The student, Yang Zhou, submitted this Thesis for approval on 2025-12-09 at 08:50.","This Thesis was approved for publication on 2025-12-09 at 13:51.","DSpace SAF Submission Ingestion Package generated from Vireo submission #23110 on 2026-02-19 at 18:46:53"]},{"key":"dc:format","label":"Dc Format","values":["application/pdf"]},{"key":"dc:title","label":"Title","values":["Demystifying CXL type-2 devices—with composable CXL-SSDS as a case study"]}]}],"canonical_facts":{"dc:contributor":["Kim, Nam Sung"],"dc:creator":["Zhou, Yang"],"dc:date":["2025-12","2025-12-09"],"dc:description":["CXL is a PCIe-based interconnect that defines three protocols for three classes of devices, each with distinct capabilities. Commercial adoption has arrived first for CXL Type-3 devices, with CXL Type-2 devices emerging afterward—making it timely to clarify CXL Type-2 device’s capabilities and applications. We first examine three core CXL Type-2 device features: cache-coherent device accelerator to host memory, device accelerator to device memory, and host CPU to device memory accesses. We then introduce CXL-AnySSD, a composable, memory-semantic CXL-SSD that exploits hardware-managed device-to-host transfers in CXL Type-2 devices. By loosely coupling DRAM with commodity SSDs, CXL-AnySSD decouples capacity from performance, supports heterogeneous SSD choices, and removes OS-managed swap overheads. We implement a CXL-AnySSD prototype on a real CXL Type-2 device and show CXL-AnySSD improves end-to-end throughput by 2.3–6.2× over OS-managed SSD swap on a vector-database workload.","Submission published under a 24 month embargo labeled 'U of I Access', the embargo will last until 2027-12-01","The student, Yang Zhou, accepted the attached license on 2025-12-09 at 08:37.","The student, Yang Zhou, submitted this Thesis for approval on 2025-12-09 at 08:50.","This Thesis was approved for publication on 2025-12-09 at 13:51.","DSpace SAF Submission Ingestion Package generated from Vireo submission #23110 on 2026-02-19 at 18:46:53"],"dc:format":["application/pdf"],"dc:identifier":["https://hdl.handle.net/2142/132701"],"dc:language":["en"],"dc:rights":["Copyright 2025 Yang Zhou"],"dc:subject":["Compute Express Link","Heterogeneous Computing"],"dc:title":["Demystifying CXL type-2 devices—with composable CXL-SSDS as a case study"],"dc:type":["text","Thesis"],"thesis:degree_discipline":["Electrical & Computer Engr"],"thesis:degree_level":["Thesis"],"thesis:degree_name":["M.S."],"thesis:institution_name":["University of Illinois Urbana-Champaign"]},"updated_at":"2026-07-22T22:25:07Z"}