{"id":{"repo_id":"uiuc","oai_identifier":"oai:www.ideals.illinois.edu:2142/130032"},"canonical_url":"https://search.dev.ndltd.org/etd/uiuc/oai:www.ideals.illinois.edu:2142/130032","repository":{"repo_id":"uiuc","name":"University of Illinois - Urbana-Champaign","base_url":"https://www.ideals.illinois.edu/oai-pmh"},"display":{"title":"Investigation of factors determining charged device model electrostatic discharge reliability of integrated circuits","abstract":"Submission published under a 24 month embargo labeled 'U of I Access', the embargo will last until 2027-08-01","abstract_html":"Submission published under a 24 month embargo labeled 'U of I Access', the embargo will last until 2027-08-01","abstract_has_math":false,"creators":["Drallmeier, Matthew"],"institution":"University of Illinois Urbana-Champaign","degree_name":"Ph.D.","degree_level":"Dissertation","degree_discipline":"Electrical & Computer Engr","degree_department":null,"school":null,"contributors":["Rosenbaum, Elyse","Schutt-Aine, Jose E","Bernhard, Jennifer T","Chen, Xu"],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2025,"date_issued":"2025-07-11","date_published":"2025-07-11","updated_at":"2026-07-22T22:25:06Z","subjects":["Electrostatic Discharge (esd)","Charged Device Model (cdm)","Integrated Circuit Reliability","Gate Oxide Breakdown"],"languages":["en","eng"],"rights":["Copyright 2025 Matthew Drallmeier"],"rights_urls":[],"identifier_entries":[]},"links":{"outbound_url":"https://hdl.handle.net/2142/130032","outbound_label":"Handle","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Rosenbaum, Elyse","Schutt-Aine, Jose E","Bernhard, Jennifer T","Chen, Xu"]},{"key":"dc:creator","label":"Author","values":["Drallmeier, Matthew"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2025-07-11","2025-08"]},{"key":"dc:type","label":"Dc Type","values":["text"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Electrical & Computer Engr"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Dissertation"]},{"key":"thesis:degree_name","label":"Degree Name","values":["Ph.D."]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["University of Illinois Urbana-Champaign"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Electrostatic Discharge (esd)","Charged Device Model (cdm)","Integrated Circuit Reliability","Gate Oxide Breakdown"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language","label":"Dc Language","values":["en","eng"]},{"key":"dc:rights","label":"Dc Rights","values":["Copyright 2025 Matthew Drallmeier"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["https://hdl.handle.net/2142/130032"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["Submission published under a 24 month embargo labeled 'U of I Access', the embargo will last until 2027-08-01","The student, Matthew Drallmeier, accepted the attached license on 2025-07-10 at 09:36.","The student, Matthew Drallmeier, submitted this Dissertation for approval on 2025-07-10 at 09:48.","This Dissertation was approved for publication on 2025-07-11 at 15:40.","DSpace SAF Submission Ingestion Package generated from Vireo submission #22480 on 2025-10-21 at 10:05:46","Electrostatic discharge (ESD) protection is required at the high-speed input/output (IO) interfaces of integrated circuits (ICs) to ensure reliability, but it adds loading capacitance that hinders performance; effective ESD designs must balance that tradeoff. A critical aspect of effective ESD design is a comprehensive understanding of the voltage and current waveforms inside an IC during an ESD event and the voltage or current level at which the devices inside the circuit will be damaged. This dissertation presents two measurement methodologies that advance our knowledge of those factors, which in turn, enhance designers’ ability to develop optimal ESD protection. The first methodology is an on chip pulse generator which can apply clean, square pulses with pulse width down to 100 ps to an integrated victim device. The on chip pulse generator is used to characterize gate dielectric breakdown on the sub ns timescale. The second methodology is an on chip probe that can read out the on chip voltage waveforms during an ESD test in real time. The probe is used to capture transient voltage waveforms at internal nodes of high speed IO circuits located in a packaged IC, providing valuable insights into their ESD reliability."]},{"key":"dc:format","label":"Dc Format","values":["application/pdf"]},{"key":"dc:title","label":"Title","values":["Investigation of factors determining charged device model electrostatic discharge reliability of integrated circuits"]}]}],"canonical_facts":{"dc:contributor":["Rosenbaum, Elyse","Schutt-Aine, Jose E","Bernhard, Jennifer T","Chen, Xu"],"dc:creator":["Drallmeier, Matthew"],"dc:date":["2025-07-11","2025-08"],"dc:description":["Submission published under a 24 month embargo labeled 'U of I Access', the embargo will last until 2027-08-01","The student, Matthew Drallmeier, accepted the attached license on 2025-07-10 at 09:36.","The student, Matthew Drallmeier, submitted this Dissertation for approval on 2025-07-10 at 09:48.","This Dissertation was approved for publication on 2025-07-11 at 15:40.","DSpace SAF Submission Ingestion Package generated from Vireo submission #22480 on 2025-10-21 at 10:05:46","Electrostatic discharge (ESD) protection is required at the high-speed input/output (IO) interfaces of integrated circuits (ICs) to ensure reliability, but it adds loading capacitance that hinders performance; effective ESD designs must balance that tradeoff. A critical aspect of effective ESD design is a comprehensive understanding of the voltage and current waveforms inside an IC during an ESD event and the voltage or current level at which the devices inside the circuit will be damaged. This dissertation presents two measurement methodologies that advance our knowledge of those factors, which in turn, enhance designers’ ability to develop optimal ESD protection. The first methodology is an on chip pulse generator which can apply clean, square pulses with pulse width down to 100 ps to an integrated victim device. The on chip pulse generator is used to characterize gate dielectric breakdown on the sub ns timescale. The second methodology is an on chip probe that can read out the on chip voltage waveforms during an ESD test in real time. The probe is used to capture transient voltage waveforms at internal nodes of high speed IO circuits located in a packaged IC, providing valuable insights into their ESD reliability."],"dc:format":["application/pdf"],"dc:identifier":["https://hdl.handle.net/2142/130032"],"dc:language":["en","eng"],"dc:rights":["Copyright 2025 Matthew Drallmeier"],"dc:subject":["Electrostatic Discharge (esd)","Charged Device Model (cdm)","Integrated Circuit Reliability","Gate Oxide Breakdown"],"dc:title":["Investigation of factors determining charged device model electrostatic discharge reliability of integrated circuits"],"dc:type":["text"],"thesis:degree_discipline":["Electrical & Computer Engr"],"thesis:degree_level":["Dissertation"],"thesis:degree_name":["Ph.D."],"thesis:institution_name":["University of Illinois Urbana-Champaign"]},"updated_at":"2026-07-22T22:25:06Z"}